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公开(公告)号：KR1020030080847A
公开(公告)日：2003-10-17
申请号：KR1020020019676
申请日：2002-04-11
Applicant: 삼성전자주식회사
IPC: H01L27/108
Abstract: PURPOSE: A semiconductor device having a capacitor and a method for manufacturing the same are provided to be capable of simplifying manufacturing processes and reducing fabrication cost by removing a wet etching process of a mold insulating layer and a sacrificial layer. CONSTITUTION: A semiconductor device having a capacitor is provided with a semiconductor substrate(101), the first layer formed at the upper portion of the resultant structure, and a capacitor hole(107b) formed through the first layer for exposing the predetermined portion of the semiconductor substrate. At this time, the first layer is formed by sequentially depositing a lower buffer insulating layer(104), a mold conductive pattern(105a), and an upper buffer insulating layer. The semiconductor device further includes an outer dielectric pattern(109a) formed at the inner wall of the capacitor hole, an outer plate electrode(108a) located between the outer dielectric pattern and the mold conductive pattern, and a storage node(120) formed at the predetermined portion of the capacitor hole.
Abstract translation: 目的：提供一种具有电容器的半导体器件及其制造方法，通过去除模具绝缘层和牺牲层的湿式蚀刻工艺，能够简化制造工艺并降低制造成本。 构成：具有电容器的半导体器件设置有半导体衬底（101），形成在所得结构的上部的第一层和形成在第一层上的电容器孔（107b），用于暴露所述第一层的预定部分 半导体衬底。 此时，通过依次沉积下缓冲绝缘层（104），模具导电图案（105a）和上缓冲绝缘层来形成第一层。 半导体器件还包括形成在电容器孔的内壁的外部电介质图案（109a），位于外部电介质图案和模具导电图案之间的外部电极（108a）和形成在外部电介质图案 电容器孔的预定部分。
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公开(公告)号：KR1020030067821A
公开(公告)日：2003-08-19
申请号：KR1020020007294
申请日：2002-02-08
Applicant: 삼성전자주식회사
IPC: H01L27/108
CPC classification number: H01L27/10855 , H01L28/91
Abstract: PURPOSE: A method for forming a capacitor of a semiconductor device is provided to be capable of preventing the fall-down of a lower electrode due to a support pattern etched when carrying out a molding pattern removing process by using an adhesive spacer made of titanium nitride. CONSTITUTION: An interlayer dielectric(100) having a contact plug(120), is formed at the upper portion of a semiconductor substrate. A supporting layer, an etch stop layer, and a molding layer are sequentially deposited on the resultant structure. A molding pattern(155) having an opening portion(250), is formed by selectively etching the molding layer for exposing the etch stop layer. An adhesive spacer(175) made of titanium nitride is formed at both sidewalls of the opening portion. An etch stop pattern(145) and a supporting pattern(135) are formed by sequentially patterning the etch stop layer and the supporting layer for exposing the contact plug. Then, a lower electrode(185) is formed on the resultant structure.
Abstract translation: 目的：提供一种用于形成半导体器件的电容器的方法，其能够通过使用由氮化钛制成的粘合剂间隔件来防止由于在进行模制图案去除处理时蚀刻的支撑图案而导致的下部电极的下降 。 构成：在半导体衬底的上部形成具有接触插塞（120）的层间电介质（100）。 在所得结构上依次沉积支撑层，蚀刻停止层和模制层。 通过选择性地蚀刻用于暴露蚀刻停止层的成型层来形成具有开口部分（250）的模制图案（155）。 在开口部分的两个侧壁处形成由氮化钛制成的粘合剂间隔物（175）。 通过顺序图案化蚀刻停止层和用于暴露接触插塞的支撑层来形成蚀刻停止图案（145）和支撑图案（135）。 然后，在所得结构上形成下电极（185）。
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公开(公告)号：KR1020030024212A
公开(公告)日：2003-03-26
申请号：KR1020010057263
申请日：2001-09-17
Applicant: 삼성전자주식회사
IPC: H01L27/04
Abstract: PURPOSE: A method of fabricating a capacitor of a semiconductor memory device for controlling a thermal budget is provided to prevent leakage current by performing a preheating process for a bottom electrode in a thermal process for crystallizing a dielectric layer. CONSTITUTION: A bottom electrode(22a) is formed on an upper surface of a semiconductor substrate(10). A thermal process for the bottom electrode(22a) is performed by using the first thermal budget. A dielectric layer(32) is formed on the bottom electrode(22a). The dielectric layer(22a) is crystallized by using the second thermal budget. The bottom electrode(22a) is formed with noble metal, conductive noble metal oxide, and conductive metal oxide. The bottom electrode(22a) is formed with Pt, Ru, Ir, PtO, RuO2, IrO2, SrRuO3, BaSrRuO3, or LaScCo.
Abstract translation: 目的：提供一种制造用于控制热量预算的半导体存储器件的电容器的方法，以通过在用于结晶电介质层的热处理中对底部电极进行预热处理来防止漏电流。 构成：在半导体衬底（10）的上表面上形成底电极（22a）。 通过使用第一热预算执行底部电极（22a）的热处理。 在底部电极（22a）上形成介电层（32）。 通过使用第二热预算使电介质层（22a）结晶。 底部电极（22a）由贵金属，导电贵金属氧化物和导电金属氧化物形成。 底部电极（22a）由Pt，Ru，Ir，PtO，RuO2，IrO2，SrRuO3，BaSrRuO3或LaScCo形成。
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公开(公告)号：KR101829003B1
公开(公告)日：2018-02-13
申请号：KR1020110024428
申请日：2011-03-18
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L27/0922 , H01L21/3003 , H01L21/823807 , H01L21/823828 , H01L29/1054 , H01L29/66651 , H01L29/7843
Abstract: 개선된피모오스성능을갖는반도체장치및 그제조방법이개시된다. 이방법은실리콘채널층및 실리콘게르마늄채널층을갖는기판을준비하고, 실리콘채널층및 실리콘게르마늄채널층상에각각배치되는게이트구조체들을형성하고, 게이트구조체가형성된결과물을덮는제 1 보호막을형성한후, 수소또는그 동위원소들중의하나를실리콘게르마늄채널층에주입하는단계를포함할수 있다. 이때, 실리콘및 실리콘게르마늄채널층들은 의채널방향을갖도록형성될수 있다.
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公开(公告)号：KR1020120018064A
公开(公告)日：2012-02-29
申请号：KR1020110071559
申请日：2011-07-19
Applicant: 삼성전자주식회사 , 엔엑스피 유에스에이, 인코포레이티드 , 글로벌파운드리즈 싱가포르 피티이 엘티디 , 인터내셔널 비즈니스 머신즈 코오퍼레이션
IPC: H01L21/8238 , H01L21/336 , H01L29/78
CPC classification number: H01L21/823807 , H01L21/28255 , H01L29/045 , H01L29/1054 , H01L29/6659 , H01L29/66651 , H01L29/7833 , H01L29/7843 , H01L29/66045
Abstract: PURPOSE: A method for forming a CMOS transistor using a tensile stress layer and a hydrogen plasma process is provided to improve an operation property of a PMOS transistor by preventing the decrease of a on-current of the PMOS transistor. CONSTITUTION: A PMOS transistor including a SiGe channel region(111) is formed. A liner layer with tensile stress is formed on the PMOS transistor. Source and drain regions of the PMOS transistor are exposed to hydrogen plasma. A tensile stress layer is formed on the PMOS transistor. A SiN layer including the tensile stress is formed on the PMOS transistor.
Abstract translation: 目的：提供使用拉伸应力层和氢等离子体处理来形成CMOS晶体管的方法，以通过防止PMOS晶体管的导通电流的降低来改善PMOS晶体管的操作性能。 构成：形成包括SiGe沟道区（111）的PMOS晶体管。 在PMOS晶体管上形成具有拉伸应力的衬垫层。 PMOS晶体管的源极和漏极区域暴露于氢等离子体。 在PMOS晶体管上形成拉伸应力层。 在PMOS晶体管上形成包括拉伸应力的SiN层。
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Patent Agency Ranking
公开(公告)号：KR1020110137435A
公开(公告)日：2011-12-23
申请号：KR1020100057372
申请日：2010-06-17
Applicant: 삼성전자주식회사
IPC: H01L21/8238
CPC classification number: H01L21/0217 , H01L21/02274 , H01L21/02326 , H01L21/823412 , H01L21/823425 , H01L21/823807 , H01L29/7843
Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to multiply a saturation drain current of PMOSFET and current driving ability using an interface oxynitride film in which compressive stress is mitigated as a buffer layer. CONSTITUTION: NMOSFET(Negative-metal Oxide Semiconductor Filed Effect Transistor)(272) and PMOSFET(Positive-metal Oxide Semiconductor Filed Effect Transistor)(274) are formed on a substrate(100). A first stress nitride pattern(322) having tensile stress is formed on the NMOSFET. An interface nitride film having second compressive stress is formed on the PMOSFET. An interface oxynitride film is formed by oxidizing the interface nitride film using plasma. A second stress nitride pattern(374) having the second compressive stress is formed on the interface oxynitride film.
Abstract translation: 目的：提供一种用于制造半导体器件的方法，其中使用压缩应力减轻为缓冲层的界面氧氮化物膜，将PMOSFET的饱和漏极电流和电流驱动能力相乘。 构成：在衬底（100）上形成NMOSFET（负金属氧化物半导体效应晶体管）（272）和PMOSFET（正金属氧化物半导体效应晶体管）（274）。 在NMOSFET上形成具有拉应力的第一应力氮化物图案（322）。 在PMOSFET上形成具有第二压应力的界面氮化物膜。 通过使用等离子体氧化界面氮化物膜来形成界面氧氮化物膜。 在界面氧氮化物膜上形成具有第二压应力的第二应力氮化物图案（374）。
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公开(公告)号：KR1020110095456A
公开(公告)日：2011-08-25
申请号：KR1020100014932
申请日：2010-02-19
Applicant: 삼성전자주식회사
Inventor： 정용국
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L21/823807 , H01L21/28255 , H01L29/1054 , H01L29/517 , H01L29/665 , H01L29/66651 , H01L29/78696
Abstract: PURPOSE: A transistor and a manufacturing method thereof are provided to improve an operation property by preventing a hole form being scattered due to tangling bond using deposition gas including reactive gas, atmospheric gas, and hydrogen gas. CONSTITUTION: A silicon germanium layer(12) is formed on the upper surface of a substrate(10). A gate oxide pattern(14a) is formed on the silicon germanium layer. A gate electrode(16a) made of metal materials is formed on the gate oxide pattern. A poly silicon pattern(18a) and a metal silicide pattern(24) are formed on the gate electrode. A spacer(20) is formed on the sidewalls of the metal silicide pattern, the gate electrode, and the poly silicon pattern.
Abstract translation: 目的：提供晶体管及其制造方法，以通过使用包括反应性气体，气氛气体和氢气的沉积气体防止由于缠结而导致的孔形成散射的操作性。 构成：在基板（10）的上表面上形成硅锗层（12）。 在硅锗层上形成栅极氧化物图案（14a）。 在栅极氧化物图案上形成由金属材料制成的栅电极（16a）。 在栅电极上形成多晶硅图案（18a）和金属硅化物图案（24）。 在金属硅化物图案，栅极电极和多晶硅图案的侧壁上形成间隔物（20）。
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公开(公告)号：KR100843246B1
公开(公告)日：2008-07-02
申请号：KR1020070049960
申请日：2007-05-22
Applicant: 삼성전자주식회사
IPC: H01L21/76 , H01L21/762
CPC classification number: H01L21/76224
Abstract: A semiconductor device having an STI(Shallow Trench Isolation) structure and a manufacturing method thereof are provided to suppress generation of a recess by forming a first and second impurity doping oxide layers on exposed parts of a sidewall oxide layer and a gap-fill oxide layer. A trench is formed on an isolation region of a substrate(100) in order to define an active region. A sidewall oxide layer(130) is formed to cover an inner wall of the trench. A nitride layer liner(140) is formed on the sidewall oxide layer. A gap-fill insulating layer(150) is formed on the nitride layer liner in order to bury the trench. A first impurity doping oxide layer is formed on an edge region of both ends of the sidewall oxide layer in order to be extended from the substrate to the nitride layer liner at an entrance of the adjacent trench on the substrate.
Abstract translation: 提供具有STI（浅沟槽隔离）结构的半导体器件及其制造方法，以通过在侧壁氧化物层和间隙填充氧化物层的暴露部分上形成第一和第二杂质掺杂氧化物层来抑制凹陷的产生 。 在衬底（100）的隔离区上形成沟槽以便限定有源区。 形成侧壁氧化物层（130）以覆盖沟槽的内壁。 氮化物层衬垫（140）形成在侧壁氧化物层上。 在氮化物层衬垫上形成间隙填充绝缘层（150）以埋入沟槽。 在侧壁氧化物层的两端的边缘区域上形成第一杂质掺杂氧化物层，以在衬底上的相邻沟槽的入口处从衬底延伸到氮化物层衬垫。
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公开(公告)号：KR100745987B1
公开(公告)日：2007-08-06
申请号：KR1020050072792
申请日：2005-08-09
Applicant: 삼성전자주식회사
IPC: H01L21/76
CPC classification number: H01L21/76224 , C23C16/045 , H01L21/02164 , H01L21/02274 , H01L21/02304 , H01L21/31608 , H01L21/31612
Abstract: 갭 충전 특성이 우수하면서 결함이 발생하지 않는 반도체 소자의 트렌치 소자 분리 방법이 제공된다. 트렌치 소자 분리 방법은 트렌치가 형성된 기판을 고밀도 플라즈마(HDP) 화학기상증착 장치에 로딩하는 단계, 기판을 제1 히트 업하는 단계, 장치에 제1 바이어스 파워를 인가하여 트렌치의 내벽과 바닥에 HDP 산화막 라이너를 형성하는 단계, 제1 바이어스 파워를 오프하고 기판을 제2 히트 업하는 단계, 제1 바이어스 파워보다 큰 제2 바이어스 파워를 인가하여 트렌치 내부 갭을 충전하는 HDP 산화막을 형성하는 단계, 및 기판을 장치로부터 언로딩하는 단계를 포함한다.
트렌치 소자 분리, 버블 결함, 라이너 분리
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