公开(公告)号：KR100534601B1

公开(公告)日：2005-12-07

申请号：KR1019990033494

申请日：1999-08-14

Applicant: 한국전자통신연구원

Inventor： 노태문 ,  이대우 ,  남기수 ,  구진근

IPC: H01L27/08

Abstract: 본 발명은 반도체 기술에 관한 것으로, 특히 제조 공정과 특성 제어가 용이한 전력 집적회로(Integrated Circuit, IC)에 관한 것이며, 그 불순물 확산 영역 형성이 용이하여, 소자의 특성을 용이하게 제어할 수 있는 구조를 가진 전력 집적회로를 제공하는데 그 목적이 있다. 본 발명은 SOI(Silicon-On-Insulator) 기판의 활성 실리콘층에 제공되는 제1 도전형-LDMOS(Lateral Double-diffused Metal Oxide Semiconductor) 트랜지스터, 제2 도전형-LDMOS 트랜지스터 및 CMOS(Complementary Metal Oxide Semiconductor) 트랜지스터를 구비한 전력 집적회로에 있어서, 상기 제1 도전형-LDMOS 트랜지스터가 상기 활성 실리콘층 내의 깊은 제2 도전형 웰에 RESURF(REduced-SURface Field)형으로 제공되며, 상기 제2 도전형-LDMOS 트랜지스터가 상기 활성 실리콘층 내의 깊은 제2 도전형 웰에 비-RESURF형으로 제공되는 것을 특징으로 한다.

公开(公告)号：KR100328126B1

公开(公告)日：2002-08-14

申请号：KR1019980051086

申请日：1998-11-26

Applicant: 한국전자통신연구원

Inventor： 남기수 ,  노태문 ,  구진근 ,  김대용

IPC: H01L29/786

Abstract: 액티브 매트릭스 액정 디스플레이( AMLCD : Active Matrix Liquid Crystal Display) 및 EL 디스플레이에서 패널의 픽셀 어레이 스윗치와 주변 구동 집적회로에 이용되는 트렌치 게이트를 구비한 다결정 실리콘 박막 트랜지스터의 제조방법이 개시된다. 본 발명은 실리콘 또는 석영, 유리기판 위에 수평으로 구성되어 있는 게이트 구조를 트렌치 기술을 이용하여 수직으로 게이트를 구성한 트렌치 게이트 구조를 갖는 다결정 실리콘 박막 트랜지스터를 제조함으로써, 소자가 차지하는 면적을 줄일 뿐만 아니라 구동 전류의 감소 없이 고 전압에서 동작 할 수 있다

公开(公告)号：KR100289055B1

公开(公告)日：2001-08-07

申请号：KR1019970061585

申请日：1997-11-20

Applicant: 한국전자통신연구원

Inventor： 김종대 ,  김상기 ,  남기수 ,  구진근

IPC: H01L29/78

Abstract: PURPOSE: A method for fabricating a P-channel double diffusion power device is provided to improve an ON-resistance by preventing diffusion of dopants of a drift region and shortening a length of the drift region. CONSTITUTION: A buried oxide layer(21) and a P-epitaxial layer(22) are laminated on a semiconductor substrate(20). A deep N-well(23) is formed on by implanting the first conductive dopant ions into the semiconductor substrate(20). An ion implantation mask is formed on the deep N-well(23) in order to define a drift region. A drift region(24) and an N-well are formed by forming an ion implantation mask for defining the N-well region and implanting the second dopants. A thermal oxide layer and a TEOS oxide layer are formed on a whole surface of the semiconductor substrate(20). A field oxide layer(26) is formed by etching the thermal oxide layer and the TEOS oxide layer. A gate oxide layer(27) and a gate electrode(28) are formed on a gate region. A source and a drain region(30,29) are formed by implanting the first conductive dopants into the active region.

公开(公告)号：KR1020010062967A

公开(公告)日：2001-07-09

申请号：KR1019990059752

申请日：1999-12-21

Applicant: 한국전자통신연구원

Inventor： 노태문 ,  이대우 ,  남기수 ,  김종대 ,  김상기 ,  구진근

IPC: H01L27/088

Abstract: PURPOSE: A high speed power transistor and a fabrication method thereof are provided to reduce the resistance of a trench gate electrode and thus to increase an operation speed of the device by reducing a transfer delay time of an electrical signal by the reduction of the resistance. CONSTITUTION: A gate is formed by stacking a polysilicon and a metal in a trench. A lightly doped N-type silicon epi layer(2) is grown on a heavily doped N-type silicon substrate(1). After growing a thin oxide on the epi layer, an N-type impurity ion is implanted to form a body(3) and is annealed. A nitride film pattern is formed on the oxide and a heavily doped N-type impurity ion is implanted and a well(4) is formed by a high temperature annealing as growing the oxide on the revealed part. And a source junction(5) is formed by implanting a heavily doped P-type impurity ion. After removing the oxide and forming an insulation film(11), a trench is formed by dry-etching the insulation film and the source junction and the body and a part of the epi layer on the gate region. After forming a gate oxide(12) in the trench, a doped polysilicon(14) and a metal(15) are stacked. After etching a part of the polysilicon and the metal, an interlayer insulation film(13) is deposited. And, an electrode contacted to each of the source junction and the metal is formed by etching the interlayer insulation film selectively, and a drain is formed under the silicon substrate.

Abstract translation: 目的：提供一种高速功率晶体管及其制造方法，以减小沟槽栅电极的电阻，从而通过降低电阻降低电信号的传输延迟时间来提高器件的工作速度。 构成：通过在沟槽中堆叠多晶硅和金属形成栅极。 在重掺杂的N型硅衬底（1）上生长轻掺杂的N型硅外延层（2）。 在epi层上生长薄氧化物后，注入N型杂质离子以形成体（3）并进行退火。 在氧化物上形成氮化物膜图案，并且注入重掺杂的N型杂质离子，并且通过在显露部分上生长氧化物的高温退火形成阱（4）。 并且通过注入重掺杂的P型杂质离子形成源极结（5）。 在去除氧化物并形成绝缘膜（11）之后，通过干蚀刻栅极区上的绝缘膜和源极结以及主体和外延层的一部分来形成沟槽。 在沟槽中形成栅极氧化物（12）之后，堆叠掺杂多晶硅（14）和金属（15）。 在蚀刻多晶硅和金属的一部分之后，沉积层间绝缘膜（13）。 并且，通过选择性地蚀刻层间绝缘膜来形成与源极结和金属中的每一个接触的电极，并且在硅衬底下方形成漏极。

公开(公告)号：KR1020010017801A

公开(公告)日：2001-03-05

申请号：KR1019990033493

申请日：1999-08-14

Applicant: 한국전자통신연구원

Inventor： 남기수 ,  김상기 ,  노태문 ,  구진근

IPC: H01L27/08

Abstract: PURPOSE: A method for manufacturing a power device is provided to reduce on-resistance by decreasing an area occupied by a unit power device, and to simplify a manufacturing process by decreasing the number of masks. CONSTITUTION: An oxide layer(3) is formed on a semiconductor substrate of the first conductivity type. The oxide layer is etched by using a trench gate mask. Ions for forming the second conductive well are implanted by using the oxide layer as an ion implantation mask. A heat treatment is performed to form the second conductive well. An ion implantation for forming a source of the high density first conductivity type is performed by using the oxide layer as an ion implantation mask. A spacer oxide layer(5) is formed on a sidewall of the oxide layer. The well of the second conductivity type is etched to form a trench by using the oxide layer and the spacer oxide layer as an etching mask, and the source of the high density first conductivity type is defined. A gate insulating layer is formed on an inner wall of the trench. A gate electrode material is buried in the trench having the gate insulating layer. A gate passivation layer is formed on the exposed gate electrode material. A source electrode(10) in contact with the source of the high density first conductivity type is formed. A drain electrode(13) in contact with a back side of the semiconductor substrate is formed.

Abstract translation: 目的：提供一种用于制造功率器件的方法，通过减小单元功率器件占用的面积来减小导通电阻，并通过减少掩模数来简化制造过程。 构成：在第一导电类型的半导体衬底上形成氧化物层（3）。 通过使用沟槽栅掩模蚀刻氧化物层。 通过使用氧化物层作为离子注入掩模来注入用于形成第二导电阱的离子。 进行热处理以形成第二导电孔。 用于形成高密度第一导电类型的源的离子注入通过使用氧化物层作为离子注入掩模进行。 间隔氧化物层（5）形成在氧化物层的侧壁上。 通过使用氧化物层和间隔氧化物层作为蚀刻掩模蚀刻第二导电类型的阱以形成沟槽，并且限定高密度第一导电类型的源。 栅极绝缘层形成在沟槽的内壁上。 栅极电极材料被埋在具有栅极绝缘层的沟槽中。 在暴露的栅极电极材料上形成栅极钝化层。 形成与高密度第一导电型的源极接触的源电极（10）。 形成与半导体基板的背面接触的漏电极（13）。

公开(公告)号：KR100275541B1

公开(公告)日：2001-01-15

申请号：KR1019970070321

申请日：1997-12-19

Applicant: 한국전자통신연구원

Inventor： 유현규 ,  박민 ,  이상국 ,  남기수

IPC: H01L27/06

Abstract: PURPOSE: A structure of a high frequency resonance circuit for arranging a capacitor in an internal diameter of an inductor and a method for designing the same are provided to reduce an area of a resonance circuit by forming an integrated inductor in an internal diameter of an inductor. CONSTITUTION: An inductor is formed with a metallic line(20) of N layer as an input terminal, metallic lines(22,26) of N-1 layer connected through a contact hole(21) of the input terminal of the metallic layer(20) and a contact hole(25) of a termination of the metallic layer(20), and an inter-metal insulating layer between a lower portion of the metallic line(20) of N layer and an upper portion of the metallic lines(22,26) of N-1 layer. A high frequency resonance circuit is formed with a polysilicon layer(28) of M layer connected with the metallic layer(26) and the contact hole(25), a polysilicon layer(24) of M-1 layer, and an inter-polysilicon insulating layer.

Abstract translation: 目的：提供一种用于布置电感器内径中的电容器的高频谐振电路的结构及其设计方法，以通过在电感器的内径中形成集成电感器来减小谐振电路的面积 。 构成：电感器由N层的金属线（20）形成为输入端子，N-1层的金属线（22,26）通过金属层的输入端子的接触孔（21）连接（ 20）和金属层（20）的端接件的接触孔（25），以及在N层金属线（20）的下部与金属线的上部之间的金属间绝缘层（ 22,26）N-1层。 高频谐振电路形成有与金属层（26）和接触孔（25）连接的M层的多晶硅层（28），M-1层的多晶硅层（24）和多晶硅 绝缘层。

公开(公告)号：KR100275494B1

公开(公告)日：2001-01-15

申请号：KR1019980016540

申请日：1998-05-08

Applicant: 한국전자통신연구원

Inventor： 이대우 ,  노태문 ,  구진근 ,  남기수

IPC: H01L29/78

Abstract: PURPOSE: A race-tack type current-controlled power device and a fabricating method thereof are provided to increase a breakdown voltage by reducing a field enhancement effect. CONSTITUTION: A p- epitaxial layer(2) is formed on a p type silicon substrate(1). A p well(3) as a channel region and an n drift region(4) are formed by performing a mask process, a dopant implantation process, and a high thermal process. A buffer oxide layer and a nitride layer are formed by performing a LOCOS(LOCal Oxidation of Silicon) process. A photo-resist layer is applied on a whole surface of the structure. A photo-resist layer pattern is defined by performing a mask process using an isolation mask. An oxide barrier pattern is formed by etching the nitride layer and the buffer oxide layer. The photo-resist layer pattern is removed. A field oxide layer(8) is grown thereon. The nitride layer and the buffer oxide layer are removed. A gate oxide layer and a polysilicon layer(10) are formed on the channel region. An n+ source(11a), a p+ source contact layer(12), and an n+ drain(11b) are formed by performing an ion implantation process. A source electrode(14), a drain electrode(15), and a gate electrode are formed by forming and etching a metal layer on the whole surface.

Abstract translation: 目的：提供一种耐磨型电流控制功率器件及其制造方法，以通过减小场增强效应来增加击穿电压。 构成：在p型硅衬底（1）上形成p-外延层（2）。 通过执行掩模处理，掺杂剂注入工艺和高热处理来形成作为沟道区和n漂移区（4）的p阱（3）。 通过执行LOCOS（硅的局部氧化）工艺来形成缓冲氧化物层和氮化物层。 在结构的整个表面上施加光刻胶层。 通过使用隔离掩模执行掩模处理来定义光刻胶层图案。 通过蚀刻氮化物层和缓冲氧化物层形成氧化物阻挡图案。 除去光致抗蚀剂图案。 在其上生长场氧化物层（8）。 去除氮化物层和缓冲氧化物层。 在沟道区上形成栅氧化层和多晶硅层（10）。 通过进行离子注入工艺来形成n +源极（11a），p +源极接触层（12）和n +漏极（11b）。 通过在整个表面上形成和蚀刻金属层来形成源电极（14），漏电极（15）和栅电极。

公开(公告)号：KR100268174B1

公开(公告)日：2000-10-16

申请号：KR1019970073705

申请日：1997-12-24

Applicant: 한국전자통신연구원

Inventor： 김종대 ,  이상용 ,  김상기 ,  노태문 ,  구진근 ,  남기수

IPC: H01L29/06

Abstract: PURPOSE: A power device for resisting high pressure having a field-limiting ring is provided to improve the breakdown voltage by adding a floating ring only in the edge region so as to prevent an electric field from concentrating into the edge region. CONSTITUTION: A plurality of field-limiting rings(24) are added on a substrate(22) by decreasing the distance between the field-limiting rings(24). The distance between the field-limiting rings(24) in the square region of the substrate(22) is designed in consideration of cylinder coordinates, while the distance in the edge region of the substrate(22) is designed in consideration of circular coordinates, so that a transition region is formed. By adding floating rings(24, 25) in the edge region, the dispersion of electric field is improved and the value of the maximum electric field is decreased.

Abstract translation: 目的：提供一种用于抵抗具有场限制环的高压的功率器件，以通过仅在边缘区域中添加浮环以提高击穿电压，以防止电场集中到边缘区域。 构成：通过减小场限制环（24）之间的距离，将多个场限制环（24）添加到衬底（22）上。 考虑到圆柱坐标来设计衬底（22）的正方形区域中的场限制环（24）之间的距离，而基于圆坐标设计衬底（22）的边缘区域中的距离， 从而形成过渡区域。 通过在边缘区域中增加浮环（24,25），改善了电场的色散，并减小了最大电场的值。

公开(公告)号：KR1020000033991A

公开(公告)日：2000-06-15

申请号：KR1019980051086

申请日：1998-11-26

Applicant: 한국전자통신연구원

Inventor： 남기수 ,  노태문 ,  구진근 ,  김대용

IPC: H01L29/786

Abstract: PURPOSE: A method for fabricating dual or multiple gate polysilicon thin film transistor is provided to allow operation in high voltage, to prevent a leakage current, and to decrease device size. CONSTITUTION: A polysilicon thin film transistor is used for a pixel array switch of panel or a drive IC in an active matrix liquid crystal display(AMLCD) device or an electroluminescence(EL) display device. The fabrication begins with a forming step of at least one trench as a vertical gate region by etching an insulating substrate(10), and then a step of successively forming an oxide layer(12) and an amorphous silicon thin film is followed. Next, a step of converting the amorphous silicon thin film into a polysilicon thin film(23) is carried out, and thereto an active layer to be used as source, drain and channel regions is formed by ion implantation. After that, a gate oxide layer(24) is formed and a trench gate electrode(25) is formed on the gate oxide layer in the trench. A field oxide layer(26) is then formed, exposing the source and drain regions in the active layer. A source electrode(28a) and a drain electrode(28b) are respectively formed into the exposed source and drain regions.

Abstract translation: 目的：提供一种用于制造双栅极或多栅极多晶硅薄膜晶体管的方法，以允许高电压工作，防止漏电流，并降低器件尺寸。 构成：多晶硅薄膜晶体管用于有源矩阵液晶显示器（AMLCD）器件或电致发光（EL）显示器件中的面板的像素阵列开关或驱动IC。 通过蚀刻绝缘基板（10），通过至少一个沟槽的形成步骤作为垂直栅极区域开始制造，然后遵循依次形成氧化物层（12）和非晶硅薄膜的步骤。 接着，进行将非晶硅薄膜转换为多晶硅薄膜（23）的工序，通过离子注入形成用作源极，漏极和沟道区域的有源层。 之后，形成栅极氧化物层（24），并且在沟槽中的栅极氧化物层上形成沟槽栅电极（25）。 然后形成场氧化物层（26），暴露有源层中的源区和漏区。 源电极（28a）和漏电极（28b）分别形成为暴露的源极和漏极区域。

公开(公告)号：KR1020000032754A

公开(公告)日：2000-06-15

申请号：KR1019980049309

申请日：1998-11-17

Applicant: 한국전자통신연구원

Inventor： 남기수 ,  노태문 ,  김상기 ,  김종대 ,  이대우 ,  구진근 ,  김대용

IPC: H01L29/78

Abstract: PURPOSE: A power device having vertical trench gates and a thick oxide layer on drift region is provided to obtain high breakdown voltage and low ON-resistance. CONSTITUTION: A high voltage power device used for a step motor, an automobile, and a plate display drive IC is fabricated. Source regions(28) are formed in both sides of a silicon substrate(20) having p-wells(25) therein, and a drain region(26) is formed in a mmiddle of the substrate(20). A trench(29) is then formed between the source and drain regions(28,26). A first thick field oxide layer(35) is formed on both a bottom surface and a side wall of the trench(29) in the drift region, and on the source and drain regions(28,26). A gate layer(37) is formed in the trench(29) surrounded by the first field oxide layer(35), and an oxide layer(36') is further formed on the gate layer(37). Moreover, a second field oxide layer(38) is formed on the oxide layers(35,36'). Source electrodes(39) and a drain electrode(40) are formed in contact holes of the first and second field oxide layer(35,38). Particularly, in the trench(29), the bottom gate oxide layer and the side wall gate oxide layer toward the drift region are thicker than the other side wall gate oxide layer toward a channel region.

Abstract translation: 目的：提供具有垂直沟槽栅极和漂移区上厚厚氧化层的功率器件，以获得高击穿电压和低导通电阻。 构成：制造用于步进电机，汽车和板显示驱动IC的高压电力装置。 源极区（28）形成在其中具有p阱（25）的硅衬底（20）的两侧，并且在衬底（20）的mm中形成漏极区（26）。 然后在源区和漏区（28,26）之间形成沟槽（29）。 第一厚氧化物层（35）形成在漂移区域中的沟槽（29）的底表面和侧壁上以及源极和漏极区域（28,26）上。 在由第一场氧化物层（35）围绕的沟槽（29）中形成栅极层（37），并且在栅极层（37）上进一步形成氧化物层（36'）。 此外，在氧化物层（35,36'）上形成第二场氧化物层（38）。 源电极（39）和漏电极（40）形成在第一和第二场氧化物层（35,38）的接触孔中。 特别地，在沟槽（29）中，底栅氧化层和侧壁栅氧化层朝向漂移区比另一侧壁栅极氧化物层朝向沟道区域厚。