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公开(公告)号：KR1019930006987A
公开(公告)日：1993-04-22
申请号：KR1019910016477
申请日：1991-09-20
Applicant: 한국전자통신연구원
IPC: H01L29/80
Abstract: 본 발명은 종래의 병렬형 게이트 단자를 가지는 양자간섭 트랜지스터 보다 우수한 간섭현상을 나타내기 위한 다기능 수직형 게이트의 양자간섭 트랜지스터의 제작에 관한 것이다.
게이트 금속 단자면을 전자의 한쪽 통로 위에 소자의 성장면과 평행하게 올려놓음으로써, 전자가 게이트 밑을 통과할때 보다 일정한 전압의 영향을 받게하여, 여러가지 전자통로에 대한 게이트 전압의 파동(fluctuation)으로 부터 발생하는 효과를 줄이고, 게이트 임계전압을 낮추고 트랜지스터의 상호 콘덕턴스(transconductance)를 높인다.-
公开(公告)号：KR100450762B1
公开(公告)日：2004-10-01
申请号：KR1020020057329
申请日：2002-09-19
Applicant: 한국전자통신연구원
IPC: H01L29/78
CPC classification number: H01L29/78696 , H01L29/66772 , H01L29/78609
Abstract: An ultra small-sized SOI MOSFET having a high integration density, low power consumption, but high performances, and a method of fabricating the same are provided. The method includes preparing a SOI substrate on which a monocrystalline silicon layer is formed, forming a first dielectric material layer doped with impurities of a first conductivity type on the SOI substrate, forming an opening to expose the monocrystalline silicon layer etching at least part of the first dielectric material layer, forming a channel region injecting impurities of a second conductivity type into the monocrystalline silicon layer exposed by the opening, forming a source region and a drain region in the monocrystalline silicon layer diffusing the impurities of the first dielectric material layer using heat treatment, forming a gate dielectric layer in the opening on the channel region, forming a gate electrode on the gate dielectric layer to fit in the opening, forming a second dielectric material layer on the entire surface of the SOI substrate on which the gate electrode is formed, forming contact holes to expose the gate electrode, the source region, and the drain region etching part of the second dielectric material layer, and forming metal interconnections to bury the contact holes.
Abstract translation: 提供了具有高集成度，低功耗，高性能的超小型SOI MOSFET及其制造方法。 该方法包括：制备在其上形成单晶硅层的SOI衬底;在SOI衬底上形成掺杂有第一导电类型的杂质的第一介电材料层;形成开口以暴露单晶硅层，从而蚀刻至少部分 第一介电材料层，形成沟道区域，将通过开口暴露的单晶硅层中的第二导电类型的杂质注入到所述单晶硅层中;在单晶硅层中形成源极区域和漏极区域，使用热量扩散第一介电材料层的杂质 在沟道区上的开口中形成栅极介电层;在栅极介电层上形成栅极以配合开口;在SOI基板的整个表面上形成第二介电材料层，其上形成有栅极 形成接触孔以暴露栅电极，源极区和漏极 区域蚀刻第二介电材料层的一部分，并形成金属互连以掩埋接触孔。
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公开(公告)号：KR1020040025376A
公开(公告)日：2004-03-24
申请号：KR1020020057329
申请日：2002-09-19
Applicant: 한국전자통신연구원
IPC: H01L29/78
CPC classification number: H01L29/78696 , H01L29/66772 , H01L29/78609
Abstract: PURPOSE: An ultra small size SOI(Silicon On Insulator) MOSFET and a method for manufacturing the same are provided to be capable of improving reliability and integration degree. CONSTITUTION: An SOI substrate with a single crystalline silicon layer is prepared. A doped first insulating layer(40) is formed on the substrate. The single crystalline silicon layer is exposed by selectively etching the first insulating layer(40). A channel region(72) is formed by implanting dopants into the exposed silicon layer. A source and drain region(32,34) are formed on the silicon layer by diffusing the dopants using annealing. A gate insulating layer(80) and a gate electrode(92) are sequentially formed on the channel region. The second insulating layer(110) is formed on the resultant structure. Contact holes are formed to expose the gate electrode, the source and drain region by selectively etching the second insulating layer. Metal lines(130,132,134) are filled in the contact holes, respectively.
Abstract translation: 目的：提供超小尺寸SOI（绝缘体上硅）MOSFET及其制造方法，以提高可靠性和集成度。 构成：制备具有单晶硅层的SOI衬底。 在衬底上形成掺杂的第一绝缘层（40）。 通过选择性地蚀刻第一绝缘层（40）来暴露单晶硅层。 通过将掺杂剂注入暴露的硅层中形成沟道区（72）。 通过使用退火扩散掺杂剂，在硅层上形成源区和漏区（32,34）。 栅极绝缘层（80）和栅电极（92）依次形成在沟道区上。 在所得结构上形成第二绝缘层（110）。 形成接触孔，以通过选择性地蚀刻第二绝缘层来露出栅极，源极和漏极区域。 金属线（130,132,134）分别填充在接触孔中。
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公开(公告)号：KR100400717B1
公开(公告)日：2003-10-08
申请号：KR1020020002497
申请日：2002-01-16
Applicant: 한국전자통신연구원
IPC: H01L21/336 , B82Y40/00
CPC classification number: H01L29/78648 , H01L21/84 , H01L27/1203 , H01L29/78654
Abstract: The present invention relates to a method of manufacturing a nano transistor. The present invention manufactures the nano transistor without changing a conventional method of forming the nano transistor formed on a SOI substrate. Further, the present invention includes forming a N well and a P well at giving regions of an underlying silicon substrate so that a given voltage can be individually applied to a NMOS transistor and a PMOS transistor. Therefore, the present invention can control the threshold voltage to prevent an increase of the leakage current.
Abstract translation: 本发明涉及一种制造纳米晶体管的方法。 本发明制造纳米晶体管而不改变形成在SOI衬底上的纳米晶体管的常规方法。 此外，本发明包括在赋予底层硅衬底的区域时形成N阱和P阱，使得可以将给定电压分别施加到NMOS晶体管和PMOS晶体管。 因此，本发明可以控制阈值电压以防止泄漏电流的增加。
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Patent Agency Ranking
公开(公告)号：KR1020030056328A
公开(公告)日：2003-07-04
申请号：KR1020010086529
申请日：2001-12-28
Applicant: 한국전자통신연구원
IPC: H01L21/203 , B82Y40/00
CPC classification number: C23C14/28 , B82Y20/00 , C23C14/16 , Y10T117/10
Abstract: PURPOSE: A method for manufacturing an Er-doped silicon nano dot array and a laser ablation equipment used for the same are provided to be capable of preventing the contamination due to impurities, and forming an Er-doped silicon layer having a high purity. CONSTITUTION: A target(1300) including a silicon region(1350) and an erbium region(1310), is prepared. A silicon substrate is loaded opposite to the surface of the target. An erbium doped silicon layer is formed on the silicon substrate by using a plum(1700) containing silicon vaporized from the silicon region and erbium vaporized from the erbium region. At this time, the plum is generated by irradiating laser beam onto the target. Then, the erbium doped silicon layer is patterned.
Abstract translation: 目的：提供一种用于制造掺铒硅纳米点阵列的方法和用于其的激光烧蚀设备，以能够防止由杂质引起的污染，并形成具有高纯度的Er掺杂硅层。 构成：制备包括硅区（1350）和铒区（1310）的靶（1300）。 硅衬底与靶的表面相对地加载。 通过使用含有从硅区蒸发的硅和从铒区蒸发的铒的含有李子（1700），在硅衬底上形成掺铒硅层。 此时，通过将激光束照射到靶上而产生李子。 然后，对掺铒硅层进行图案化。
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公开(公告)号：KR100384892B1
公开(公告)日：2003-05-22
申请号：KR1020000072320
申请日：2000-12-01
Applicant: 한국전자통신연구원
IPC: H01L21/203
CPC classification number: C23C14/0652 , C23C14/28 , C30B23/002 , C30B29/06 , H01L21/02381 , H01L21/02532 , H01L21/02581 , H01L21/0259 , H01L21/02631 , H01L21/02667 , H01L21/30604 , H01L21/3081 , H01L21/3086 , H01L21/31116 , H01L29/167
Abstract: An apparatus for fabricating silicon thin films for use in laser ablation includes a silicon substrate rotatably mounted in a process chamber maintaining a ultra high vacuum, pulsed light source means mounted outside the process chamber for emitting a pulsed light beam, target rotating means mounted in the process chamber for rotating a plurality of targets mounted therein, the targets being made of a different material, light beam splitting means for splitting the pulsed light beam into double light beams of the same intensity, light beam intensity regulating means for regulating the intensity of the double light beams, wherein the targets are mounted to face the silicon substrate so as, to uniformly overlap the vaporization products of the targets generated by irradiating the double light beams on the silicon substrate.
Abstract translation: 一种用于制造用于激光烧蚀的硅薄膜的设备包括：可旋转地安装在保持超高真空的处理室中的硅衬底;安装在处理室外部用于发射脉冲光束的脉冲光源装置;安装在处理室中的目标旋转装置， 处理室，用于旋转安装在其中的多个目标，目标由不同材料制成;光束分离装置，用于将脉冲光束分成相同强度的双光束;光束强度调节装置，用于调节 双光束，其中目标被安装成面对硅基板，从而均匀地重叠通过照射双光束在硅基板上产生的目标的汽化产物。
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公开(公告)号：KR100346778B1
公开(公告)日：2002-08-01
申请号：KR1019990032698
申请日：1999-08-10
Applicant: 한국전자통신연구원
IPC: H01L29/786 , B82Y40/00
Abstract: 본발명은단전자트랜지스터의제조방법에관한것으로, SIMOX(Separation by IMplanted OXygen) 기판에활성영역패턴을형성하는제 1공정과, 게이트콘텍을형성하고소오스, 드레인채널영역을위한이온주입을하는제 2공정과, 상기활성영역패턴을서로꼭지점이마주보는두개의채널패턴으로분리형성하고, 상기매립된실리콘산화막층의상면에사이드게이트를형성하는제 3공정과; 소오스, 드레인콘텍을형성하고, 상기두개의채널패턴의꼭지점과상기사이드게이트의사이에알루미늄양자점을형성하는제 4공정을수행하는단전자트랜지스터제조방법을제공한다. 상기제 4공정은전자리소그라피로금속증착영역을가능한작게(100nm x 100nm) 패턴한후 수나노미터두께의알루미늄을증착한다. 수나노미터두께의알루미늄박막은스스로수 나노미터크기의금속클러스터를형성하므로이러한클러스터를소오스와드레인사이의양자점으로이용하여다중양자점을통한다중접합채널과사이드게이트(side gate)로전자흐름의제어로단전자트랜지스터를제작할 수있다.
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公开(公告)号：KR100301116B1
公开(公告)日：2001-10-20
申请号：KR1019980052529
申请日：1998-12-02
Applicant: 한국전자통신연구원
IPC: H01L21/82
Abstract: 본 발명은 양자점 구조를 갖는 화합물반도체 기판의 제조 방법에 관한 것이다.
본 발명은 기판상에 다수의 유전체 박막 패턴을 형성하는 단계와; 상기 다수의 유전체 박막 패턴을 포함하는 기판의 노출된 영역상에 피라미드 형태의 버퍼층 및 장벽층을 차례로 형성하는 단계와; 상기 각각의 장벽층상에 Ga 드롭렛을 형성하는 단계와; 상기 Ga 드롭렛을 GaAs 양자점으로 전환시키는 단계와; 양자효과를 위해, 상기 기판에 열처리를 실시한 후, 상기 GaAs 양자점을 감싸는 보호층을 형성하는 단계를 포함하여 이루어지며, 원하는 위치에 정렬시킨 양자점을 형성하는 양자점 구조(quantum dot)를 간단한 공정을 이용하여 제작하여 반도체 레이저(laser)와 같은 광소자나 트랜지스터 및 기억소자와 같은 전자소자에 이용할 수 있는 양자점 구조를 갖는 화합물반도체 기판의 제조 방법을 제안하고자 한다.-
公开(公告)号：KR100250460B1
公开(公告)日：2000-04-01
申请号：KR1019970047170
申请日：1997-09-12
Applicant: 한국전자통신연구원
IPC: H01L21/318
Abstract: PURPOSE: A method for manufacturing a silicon quantum wire is provided to observe a quantum phenomenon in a high temperature by forming a quantum wire surrounded with a silicon oxide layer and a silicon nitride layer. CONSTITUTION: A silicon nitride layer(4) is formed on an upper portion of a SIMOX(Separation by IMplanted Oxygen) substrate laminated with a silicon substrate(1), the first silicon oxide layer(2), and a silicon layer(3). A selected region of the silicon nitride layer(4) is removed. A part of the silicon layer(3) is removed by using the remaining silicon nitride layer(4) as a shielding layer. The second silicon oxide layer(6) is grown on a side face of the silicon layer(3).
Abstract translation: 目的：提供一种制造硅量子线的方法，通过形成由氧化硅层和氮化硅层包围的量子线来观察高温下的量子现象。 构成：在层叠有硅衬底（1），第一氧化硅层（2）和硅层（3）的SIMOX（通过掺入氧分离）衬底的上部形成氮化硅层（4） 。 去除氮化硅层（4）的选定区域。 通过使用剩余的氮化硅层（4）作为屏蔽层来去除硅层（3）的一部分。 在硅层（3）的侧面上生长第二氧化硅层（6）。
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