公开(公告)号：JP2010098746A

公开(公告)日：2010-04-30

申请号：JP2009269334

申请日：2009-11-26

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： WONG WILSON ,  RAKESH PATEL H ,  SHUMARAYEV SERGEY ,  LAI TIN H

IPC: H04B3/04 ,  H03K19/0175 ,  H03K19/094 ,  H03K19/0952 ,  H04L25/03

CPC classification number: H04B7/005 ,  H04L25/03006 ,  H04L25/061

Abstract: PROBLEM TO BE SOLVED: To provide a technology for adjusting a digital signal received from a communication path.
SOLUTION: Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver receives a signal from a communication path which attenuates at least some frequency components of the signal. The receiver includes an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于调整从通信路径接收的数字信号的技术。 公开了用于调整从通信路径接收的信号的系统和方法。 接收机从通信路径接收信号，该信号衰减信号的至少一些频率分量。 接收机包括调整接收信号的频率内容中的至少一些的均衡块，提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。 在一个实施例中，控制块控制用于高频而不是低频的均衡块中的频率调整。 对于低频调整，控制块控制信号归一化块中的归一化信号幅度。 以这种方式，在信号归一化块中执行低频内容的受控调整。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2007097160A

公开(公告)日：2007-04-12

申请号：JP2006240927

申请日：2006-09-06

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： LAI TIN ,  SHUMARAYEV SERGEY ,  MAANGAT SIMARDEEP ,  WONG WILSON

IPC: H04B3/06

CPC classification number: H03G3/3089 ,  H04L25/03885

Abstract: PROBLEM TO BE SOLVED: To accurately adjust the amount of gain in equalization circuitry. SOLUTION: Equalization circuitry (200) may be used to compensate for the attenuation of a data signal caused by a transmission medium. The control circuitry for the equalization circuitry may generate control inputs for equalization stages (202) that control the amount of gain provided to the data signal. A comparator (212) may determine whether the gain from the equalization circuitry is less than or more than the desired amount of gain. A programmable up/down counter (204) may adjust the counter value based on the output of the comparator. The counter value may be converted into one or more analog voltages using one or more digital-to-analog converters (208, 210). The analog voltages may be provided to the equalization stages as control inputs. The control circuitry may also include hysteresis circuitry (214) that prevents the counter value from being adjusted when the gain produced by the equalization stages is close to the desired amount of gain. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：准确调整均衡电路中的增益量。 解决方案：均衡电路（200）可用于补偿由传输介质引起的数据信号的衰减。 用于均衡电路的控制电路可以产生用于控制提供给数据信号的增益量的均衡级（202）的控制输入。 比较器（212）可以确定来自均衡电路的增益是否小于或大于期望的增益量。 可编程上/下计数器（204）可以基于比较器的输出来调整计数器值。 可以使用一个或多个数模转换器（208,210）将计数器值转换成一个或多个模拟电压。 模拟电压可以作为控制输入提供给均衡级。 控制电路还可以包括滞后电路（214），当由均衡级产生的增益接近期望的增益量时，阻止计数器值被调整。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：EP2553817A4

公开(公告)日：2016-11-16

申请号：EP11759912

申请日：2011-03-15

Applicant: ALTERA CORP

Inventor： DING WEIQI ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  ATESOGLU ALI ,  IPPILI SHARAT BABU

IPC: H03L7/099 ,  H01F17/00

CPC classification number: H03B5/1212 ,  H01F2021/125 ,  H01F2027/2809 ,  H01L2924/0002 ,  H03B5/1243 ,  H03B5/1268 ,  H01L2924/00

Abstract: Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.

公开(公告)号：EP2332304A4

公开(公告)日：2014-07-30

申请号：EP09818103

申请日：2009-09-29

Applicant: ALTERA CORP

Inventor： SHUMARAYEV SERGEY ,  WONG WILSON

IPC: H04L27/01 ,  H04B3/04 ,  H04L1/20 ,  H04L25/03

CPC classification number: H04L25/03885 ,  H04B3/04 ,  H04L1/205 ,  H04L25/03019

Abstract: Circuitry for receiving a serial data signal (e.g., a high-speed serial data signal) includes adjustable equalizer circuitry for producing an equalized version of the serial data signal. The equalizer circuitry may include controllably variable DC gain and controllably variable AC gain. The circuitry may further include eye height and eye width monitor circuitry for respectively producing first and second output signals indicative of the height and width of the eye of the equalized version. The first output signal may be used in control of the DC gain of the equalizer circuitry, and the second output signal may be used in control of the AC gain of the equalizer circuitry.

公开(公告)号：EP2332258A4

公开(公告)日：2014-02-26

申请号：EP09815015

申请日：2009-09-11

Applicant: ALTERA CORP

Inventor： HOANG TIM TRI ,  WONG WILSON ,  SHUMARAYEV SERGEY

IPC: H03L7/193 ,  H03L7/087

CPC classification number: H03L7/099 ,  H03L7/18

公开(公告)号：EP2345152A4

公开(公告)日：2013-02-27

申请号：EP09819718

申请日：2009-10-05

Applicant: ALTERA CORP

Inventor： SHUMARAYEV SERGEY ,  WONG WILSON ,  CHAN ALLEN ,  ATESOGLU ALI

IPC: H03B5/08 ,  H03B5/12

CPC classification number: H03B5/1228 ,  H03B5/1215 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2201/011

公开(公告)号：JP2014099925A

公开(公告)日：2014-05-29

申请号：JP2014030247

申请日：2014-02-20

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： HOANG TIM TRI ,  WONG WILSON ,  SHUMARAYEV SERGEY

IPC: H03L7/197 ,  H03L7/08 ,  H03L7/199

CPC classification number: H03L7/099 ,  H03L7/18

Abstract: PROBLEM TO BE SOLVED: To provide a technique for generating a fractional clock signal.SOLUTION: A circuit includes a phase detection circuit, a clock signal generation circuit, a first frequency divider and a second frequency divider. The phase detection circuit compares an input clock signal with a feedback signal to generate a control signal. The clock signal generation circuit generates a periodic output signal in response to the control signal. The first frequency divider divides a frequency of the periodic output signal by a first value to generate a first frequency-divided signal. The second frequency divider divides the frequency of the periodic output signal by a second value to generate a second frequency-divided signal. The first and second frequency-divided signals are routed to the phase detection circuit as the feedback signal during different time intervals.

Abstract translation: 要解决的问题：提供一种用于产生分数时钟信号的技术。解决方案：电路包括相位检测电路，时钟信号产生电路，第一分频器和第二分频器。 相位检测电路将输入时钟信号与反馈信号进行比较以产生控制信号。 时钟信号产生电路响应于控制信号产生周期性输出信号。 第一分频器将周期性输出信号的频率除以第一值以产生第一分频信号。 第二分频器将周期性输出信号的频率除以第二值，以产生第二分频信号。 在不同的时间间隔期间，第一和第二分频信号作为反馈信号被路由到相位检测电路。

公开(公告)号：JP2014064328A

公开(公告)日：2014-04-10

申请号：JP2013268773

申请日：2013-12-26

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： WONG WILSON ,  CHAN DORIS PO CHING ,  SHUMARAYEV SERGEY ,  MAANGAT SIMARDEEP ,  HOANG TIM TRI ,  LAI TIN H ,  TRAN THUNGOC M

IPC: H04L25/03 ,  H04B3/04

CPC classification number: H04L25/03885

Abstract: PROBLEM TO BE SOLVED: To provide a digital adaptive circuit network and a method for a programmable logic device.SOLUTION: A method controls equalization of an incoming data signal. The method comprises steps of: detecting bits having two consecutive different values out of the data signal; determining whether transition in the incoming data signal between the two bits is relatively low in speed or relatively high in speed; and increasing the equalization of the incoming data signal when the transition is relatively low in speed.

Abstract translation: 要解决的问题：提供数字自适应电路网络和可编程逻辑器件的方法。解决方案：一种控制输入数据信号的均衡的方法。 该方法包括以下步骤：从数据信号中检测具有两个连续不同值的位; 确定两个比特之间的输入数据信号中的转换是相对低的速度还是相对较高的速度; 并且当转换速度相对较低时，增加输入数据信号的均衡。

公开(公告)号：JP2013102456A

公开(公告)日：2013-05-23

申请号：JP2012275471

申请日：2012-12-18

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： SHUMARAYEV SERGEY ,  WONG WILSON ,  CHAN ALLEN ,  ALI ATESOGLU

IPC: H03B5/08 ,  H03B5/12 ,  H03L7/099

CPC classification number: H03B5/1228 ,  H03B5/1215 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2201/011

Abstract: PROBLEM TO BE SOLVED: To provide techniques which allow use of option conductors to connect components in an oscillator circuit.SOLUTION: An oscillator circuit 200 includes transistors that are cross-coupled through routing conductors in a first conductive layer. The oscillator circuit also includes varactors 203 to 206, capacitors 221 to 226, and option conductors 207, 208, and 212 to 216 in a second conductive layer. The option conductors each form at least a portion of a connection between one of the transistors and one of a capacitor and a varactor. The oscillator circuit may further include an inductor coupled to one of a plurality of first transistors through the routing conductors in the first conductive layer, and a second option conductor in the second conductive layer that forms a first portion of the inductor.

Abstract translation: 要解决的问题：提供允许使用选项导体连接振荡器电路中的组件的技术。 解决方案：振荡器电路200包括通过第一导电层中的布线导体交叉耦合的晶体管。 振荡器电路还包括第二导电层中的可变电抗器203至206，电容器221至226以及选项导体207,208和212至216。 选项导体各自形成晶体管之一和电容器和变容二极管之一之间的连接的至少一部分。 振荡器电路还可以包括通过第一导电层中的路由导体耦合到多个第一晶体管中的一个的电感器，以及形成电感器的第一部分的第二导电层中的第二选择导体。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2012235468A

公开(公告)日：2012-11-29

申请号：JP2012104825

申请日：2012-05-01

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： CHAN ALLEN ,  WONG WILSON

IPC: H04L25/03 ,  H03K19/0175 ,  H03K19/0948 ,  H03K19/177 ,  H04L25/02

CPC classification number: H04B3/06 ,  H04L25/0272 ,  H04L25/03343

Abstract: PROBLEM TO BE SOLVED: To provide a transmitter circuit that reduces voltage jitter of data transmission.SOLUTION: A transmitter circuit comprises: a first current source; a first filter that is connected between the first current source and a first node; a second filter that is connected between the first current source and a second node; a second current source; a third filter that is connected between the second current source and a third node; a fourth filter that is connected between the second current source and a fourth node; a driver switch circuit that are connected to the first, second, third and fourth nodes; and the like.

Abstract translation: 要解决的问题：提供减少数据传输的电压抖动的发射机电路。 解决方案：发射机电路包括：第一电流源; 连接在第一电流源和第一节点之间的第一滤波器; 连接在第一电流源和第二节点之间的第二滤波器; 第二个电流源; 连接在第二电流源和第三节点之间的第三滤波器; 连接在第二电流源和第四节点之间的第四滤波器; 驱动器开关电路，其连接到所述第一，第二，第三和第四节点; 等等。 版权所有（C）2013，JPO＆INPIT