公开(公告)号：DE112020000146T5

公开(公告)日：2021-09-09

申请号：DE112020000146

申请日：2020-01-16

Applicant: IBM

Inventor： RAISCH CHRISTOPH ,  KRAEMER MARCO ,  LEHNERT FRANK ,  KLEIN MATTHIAS ,  BRADBURY JONATHAN ,  JACOBI CHRISTIAN ,  BELMAR BRENTON ,  DRIEVER PETER

IPC: G06F13/10 ,  G06F13/20

Abstract: Ein Datenverarbeitungssystem (210) und ein Verfahren zur Handhabung einer Eingabe-/ Ausgabe-Speicheranweisung (30), das ein Systemnest (18) aufweist, welches durch einen Eingabe-/Ausgabebuscontroller (20) mit mindestens einem Eingabe-/Ausgabebus (22) verbunden ist. Eine Datenverarbeitungseinheit (216) ist über einen Aggregationspuffer (16) mit dem Systemnest (18) verbunden. Ein Systemnest (18) ist so konfiguriert, dass es Daten aus/in mindestens einer externen Einheit (214) asynchron lädt und/oder speichert. Die Datenverarbeitungseinheit (216) ist so konfiguriert, dass sie die Eingabe-/Ausgabe-Speicheranweisung (30) abschließt, bevor eine Ausführung der Eingabe-/Ausgabe-Speicheranweisung (30) in dem Systemnest (18) abgeschlossen ist. Eine asynchrone Kern-Nest-Schnittstelle (14) weist ein Eingabe-/Ausgabe-Statusarray (44) mit mehreren Eingabe-/ Ausgabe-Statuspuffern (24) auf. Eine System-Firmware (10) weist einen Wiederholungspuffer (52) auf, und der Kern (12) weist eine Analyse- und Wiederholungslogik (54) auf.

公开(公告)号：AU2020214661A1

公开(公告)日：2021-06-10

申请号：AU2020214661

申请日：2020-01-14

Applicant: IBM

Inventor： RAISCH CHRISTOPH ,  KRAEMER MARCO ,  LEHNERT FRANK ,  KLEIN MATTHIAS ,  BRADBURY JONATHAN ,  JACOBI CHRISTIAN ,  BELMAR BRENTON ,  DRIEVER PETER

IPC: G06F9/30 ,  G06F13/00 ,  G06F13/20

Abstract: A data processing system (210) and a method for handling an input/output store instruction (30), comprising a system nest (18) communicatively coupled to at least one input/output bus (22) by an input/output bus controller (20). The data processing system (210) further comprises at least a data processing unit (216) comprising a core (12), a system firmware (10) and an asynchronous core-nest interface (14). The data processing unit (216) is communicatively coupled to the system nest (18) via an aggregation buffer (16). The system nest (18) is configured to asynchronously load from and/or store data to an external device (214) which is communicatively coupled to the input/output bus (22). The data processing unit (216) is configured to complete the input/output store instruction (30) before an execution of the input/output store instruction (30) in the system nest (18) is completed.

公开(公告)号：SG11202104428PA

公开(公告)日：2021-05-28

申请号：SG11202104428P

申请日：2020-01-14

Applicant: IBM

Inventor： RAISCH CHRISTOPH ,  KRAEMER MARCO ,  LEHNERT FRANK ,  KLEIN MATTHIAS ,  BRADBURY JONATHAN ,  JACOBI CHRISTIAN ,  DRIEVER PETER ,  BELMAR BRENTON

IPC: G06F13/20 ,  G06F9/30

Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers.

公开(公告)号：SG11202104106WA

公开(公告)日：2021-05-28

申请号：SG11202104106W

申请日：2020-01-23

Applicant: IBM

Inventor： GIAMEI BRUCE ,  KLEIN MATTHIAS ,  SLEGEL TIMOTHY ,  FARRELL MARK ,  SOFIA ANTHONY ,  WEISHAUPT SIMON ,  MISHRA ASHUTOSH

IPC: G06F9/30

Abstract: A DEFLATE Conversion Call general-purpose processor instruction. An instruction is obtained by a general-purpose processor of the computing environment. The instruction is a single architected instruction of an instruction set architecture that complies to an industry standard for compression. The instruction is executed, and the executing includes transforming, based on a function to be performed by the instruction being a compression function or a decompression function, state of input data between an uncompressed form of the input data and a compressed form of the input data to provide a transformed state of data. The transformed state of the data is provided as output to be used in performing a task.

公开(公告)号：CA3127864A1

公开(公告)日：2020-08-06

申请号：CA3127864

申请日：2020-01-23

Applicant: IBM

Inventor： GIAMEI BRUCE CONRAD ,  SOFIA ANTHONY THOMAS ,  KLEIN MATTHIAS ,  WEISHAUPT SIMON ,  FARRELL MARK ,  SLEGEL TIMOTHY ,  MISHRA ASHUTOSH ,  JACOBI CHRISTIAN

IPC: G06F9/30

Abstract: An instruction to perform a function of a plurality of functions is obtained. The instruction is a single architected instruction of an instruction set architecture that complies to an industry standard for compression. The instruction is executed, and the executing includes performing the function specified by the instruction. The performing includes, based on the function being a compression function or a decompression function, transforming state of input data between an uncompressed form of the input data and a compressed form of the input data to provide a transformed state of data accessing. During performing the function, history relating to the function is accessed. The history is to be used in transforming the state of input data between the uncompressed form and the compressed form.

公开(公告)号：CA3127840A1

公开(公告)日：2020-08-06

申请号：CA3127840

申请日：2020-01-14

Applicant: IBM

Inventor： RAISCH CHRISTOPH ,  KRAEMER MARCO ,  LEHNERT FRANK ,  KLEIN MATTHIAS ,  BRADBURY JONATHAN ,  JACOBI CHRISTIAN ,  BELMAR BRENTON ,  DRIEVER PETER

IPC: G06F9/30 ,  G06F13/20

Abstract: A data processing system (210) and a method for handling an input/output store instruction (30), comprising a system nest (18) communicatively coupled to at least one input/output bus (22) by an input/output bus controller (20). The data processing system (210) further comprises at least a data processing unit (216) comprising a core (12), a system firmware (10) and an asynchronous core-nest interface (14). The data processing unit (216) is communicatively coupled to the system nest (18) via an aggregation buffer (16). The system nest (18) is configured to asynchronously load from and/or store data to at least one external device (214) which is communicatively coupled to the input/output bus (22). The data processing unit (216) is configured to complete the input/output store instruction (30) before an execution of the input/output store instruction (30) in the system nest (18) is completed. The asynchronous core-nest interface (14) comprises an input/output status array (44) with multiple input/output status buffers (24).

公开(公告)号：GB2455010A

公开(公告)日：2009-06-03

申请号：GB0822774

申请日：2008-12-15

Applicant: IBM

Inventor： KLEIN MATTHIAS ,  KOENIG ANDREAS ,  FRITZ ROLF

IPC: G06F11/07

Abstract: A method/apparatus for controlling an error handling procedure in a digital circuit with control logic comprises a plurality of control logic circuits 20 grouped into a number of error handling domains 26, 28. Each error handling domain 26, 28 is associated with a predetermined data flow of the digital circuit. The digital circuit comprises an extended error reporting unit 24 for receiving an indication of an error 30 in the control logic. The extended error reporting unit 24 includes a mask system for mapping the single errors onto error handling procedures. The digital circuit comprises an error handling unit 22 for performing the operations of the error handling procedure on the according component of the digital circuit. The control logic circuits could be implemented using finite state machines. This error handling system enables all errors to be handled using well-tested error handling procedures instead of being handled locally.