公开(公告)号：AU2003287361A1

公开(公告)日：2004-09-28

申请号：AU2003287361

申请日：2003-10-28

Applicant: IBM

Inventor： VOLANT RICHARD P ,  FLORKEY JOHN E ,  GROVES ROBERT A

IPC: B81B3/00 ,  H01F7/06 ,  H01F7/14 ,  H01H59/00 ,  H03K17/965

Abstract: A micro-electro mechanical (MEM) switch capable of inductively coupling and decoupling electrical signals is described. The inductive MEM switch consists of a first plurality of coils on a movable platform and a second plurality of coils on a stationary platform or substrate, the coils on the movable platform being above or below those in the stationary substrate. Coupling and decoupling occurs by rotating or by laterally displacing the coils of the movable platform with respect to the coils on the stationary substrate. Diverse arrangements of coils respectively on the movable and stationary substrates allow for a multi-pole and multi-position switching configurations. The MEM switches described eliminate problems of stiction, arcing and welding of the switch contacts. The MEMS switches of the invention can be fabricated using standard CMOS techniques.

公开(公告)号：AU2003278176A1

公开(公告)日：2004-05-13

申请号：AU2003278176

申请日：2003-09-18

Applicant: IBM

Inventor： CHINTHAKINDI ANIL K ,  GROVES ROBERT A ,  STEIN KENNETH J ,  SUBBANNA SESHADRI ,  VOLANT RICHARD P

IPC: B81B7/00 ,  B81C1/00 ,  H01G5/011 ,  H01G5/18 ,  H03J3/18 ,  B81B3/00

Abstract: A three-dimensional micro- electromechanical (MEM) varactor is described wherein a movable beam and fixed electrode are respectively fabricated on separate substrates coupled to each other. The movable beam with comb-drive electrodes are fabricated on the "chip side" while the fixed bottom electrode is fabricated on a separated substrate "carrier side". Upon fabrication of the device on both surfaces of the substrate, the chip side device is diced and "flipped over", aligned and joined to the "carrier" substrate to form the final device. Comb-drive (fins) electrodes are used for actuation while the motion of the electrode provides changes in capacitance. Due to the constant driving forces involved, a large capacitance tuning range can be obtained. The three dimensional aspect of the device avails large surface area. When large aspect ratio features are provided, a lower actuation voltage can be used. Upon fabrication, the MEMS device is completely encapsulated, requiring no additional packaging of the device. Further, since alignment and bonding can be done on a wafer scale (wafer scale MEMS packaging), an improved device yield can be obtained at a lower cost.

公开(公告)号：CA2828498A1

公开(公告)日：2012-12-27

申请号：CA2828498

申请日：2012-06-19

Applicant: IBM

Inventor： ANDRY PAUL S ,  FAROOQ MUKTA G ,  HANNON ROBERT ,  IYER SUBRAMANIAN S ,  KINSER EMILY R ,  TSANG CORNELIA K ,  VOLANT RICHARD P

IPC: H01L21/28 ,  H01L21/768

Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.

公开(公告)号：GB2492026A

公开(公告)日：2012-12-19

申请号：GB201218457

申请日：2011-03-03

Applicant: IBM

Inventor： FAROOQ MUKTA G ,  PETRARCA KEVIN S ,  VOLANT RICHARD P

IPC: H01L25/00 ,  H01L21/683

Abstract: A temporary substrate (901) having an array of first solder pads (192) is bonded to the front side of a first substrate (101) by reflowing an array of first solder balls (250). The first substrate (101) is thinned by removing the back side, and an array of second solder pads (142) is formed on the back side surface of the first substrate (101). The assembly of the first substrate (101) and the temporary substrate (901) is diced to form a plurality of stacks, each including an assembly of a first semiconductor chip (100) and a handle portion (900). A second semiconductor chip (200) is bonded to an assembly through an array of the second solder balls (150). The handle portion (900) is removed from each assembly by reflowing the array of the first solder balls (250), while the array of the second solder balls (150) does not refiow. The assembly is subsequently mounted on a packaging substrate (300) employing the array of the first solder balls (250).

公开(公告)号：DE112010004204T5

公开(公告)日：2012-08-30

申请号：DE112010004204

申请日：2010-10-14

Applicant: IBM

Inventor： VOLANT RICHARD P ,  FAROOQ MUKTA ,  FINDEIS PAUL F ,  PETRARCA KEVIN S

IPC: H01L21/768

Abstract: Eine Silizium-Durchkontaktierungs(TSV)-Struktur, die eine einzige koaxiale oder triaxiale Kopplung innerhalb des Siliziumsubstrats 40 bildet. Die TSV-Struktur wird mit zwei oder mehr unabhängigen elektrischen Leitern 50, 80 bereitgestellt, die voneinander und von dem Substrat isoliert sind. Die elektrischen Leiter können mit unterschiedlichen Spannungen oder Massen verbunden werden, wodurch es möglich ist, die TSV-Struktur als eine koaxiale oder triaxiale Vorrichtung zu betreiben. Mehrere Schichten unter Verwendung verschiedener Materialien können als Isolator verwendet werden, wobei die Schichten bezogen auf dielektrische Eigenschaften, Füll-Eigenschaften, Grenzflächenhaftung, CTE-Übereinstimmung und dergleichen ausgewählt werden. Die TSV-Struktur überwindet Mängel in der äußeren Isolierschicht, die zu Leckstellen führen können. Ein Verfahren zur Herstellung einer solchen TSV-Struktur wird ebenfalls beschrieben.

公开(公告)号：PL206924B1

公开(公告)日：2010-10-29

申请号：PL37781603

申请日：2003-10-28

Applicant: IBM

Inventor： VOLANT RICHARD P ,  FLORKEY JOHN E ,  GROVES ROBERT A

IPC: H01F21/04 ,  B81B3/00 ,  B81B5/00 ,  H01F7/06 ,  H01F7/14 ,  H01H59/00 ,  H03K17/965

公开(公告)号：DE112011100120B4

公开(公告)日：2016-03-17

申请号：DE112011100120

申请日：2011-01-17

Applicant: IBM

Inventor： VOLANT RICHARD P ,  FAROOQ MUKTA G ,  PETRARCA KEVIN S

IPC: H01L21/768 ,  H01L23/48 ,  H01L25/065

Abstract: Verfahren, um ein Durchgangsloch durch eine gestapelte Halbleiterwafer-Anordnung zu erzeugen, umfassend: einen ersten Halbleiterwafer (110) mit einer ersten Oberfläche (112), ein dielektrisches Material, das an der ersten Oberfläche (112) freigelegt ist und metallische Strukturen (115), die an der ersten Oberfläche (112) freigelegt sind und von dem dielektrischen Material abstehen; ein zweiter Halbleiterwafer (150) mit einer zweiten Oberfläche (114), einem Halbleitermaterial, das an der zweiten Oberfläche (114) freigelegt ist, und metallische Strukturen (155), die an der zweiten Oberfläche (114) freigelegt sind und weg von dem Halbleitermaterial abstehen, wobei die zweite Oberfläche (114) der ersten Oberfläche (112) zugewandt ist und die metallischen Strukturen (115) des zweiten Halbleiterwafers (150) mit den metallischen Strukturen (155) des ersten Halbleiterwafers (110) vereinigt sind, und eine Lücke (195) im Grenzflächenbereich zwischen der angrenzenden zugewandten ersten und zweiten Oberfläche (112, 114) existiert, wobei das Verfahren umfasst: a) Ätzung eines Loches (200), das sich durch den ersten Wafer (110) und durch die Lücke (195) erstreckt bis die zweite Oberfläche (114) des zweiten Wafers (150) teilweise freiliegt, wobei das Loch (200) eine erste Wand (210) aufweist, die sich in vertikaler Richtung (212) erstreckt und eine zweite Wand (215) aufweist, die einwärts mit einer Neigung von der ersten Wand (210) zu einer inneren Öffnung (192) in der ersten Oberfläche (112) weggeht, wobei die zweite Oberfläche (114) durch die innere Öffnung (192) freigelegt ist; b) Leitung von Teilchen in das Loch (200) und Sputtern von Halbleitermaterial (400) von mindestens einem der ...

公开(公告)号：GB2489341B

公开(公告)日：2015-01-07

申请号：GB201209074

申请日：2011-01-17

Applicant: IBM

Inventor： VOLANT RICHARD P ,  FAROOQ MUKTA G ,  PETRARCA KEVIN S

IPC: H01L21/768 ,  H01L23/48 ,  H01L25/065

Abstract: A microelectronic assembly having a through hole extending through a first wafer (or chip) and a second wafer (or chip) are provided. The first and second wafers (or chips) have confronting faces and metallic features at the faces which are joined together to assemble the first and second wafers (or chips) leaving a gap between the confronting faces. A hole is etched in the first wafer (or chip), then material is sputtered to form a wall of material in the gap between wafers (or chips). Etching continues to extend the hole into or through the second wafer (or chip). The hole is filled to form a substantially vertical through silicon conductive via.

公开(公告)号：GB2505576A

公开(公告)日：2014-03-05

申请号：GB201318982

申请日：2012-06-19

Applicant: IBM

Inventor： ANDRY PAUL S ,  FAROOQ MUKTA G ,  HANNON ROBERT ,  IYER SUBRAMANIAN S ,  KINSER EMILY R ,  TSANG CORNELIA K ,  VOLANT RICHARD P

IPC: H01L23/48 ,  H01L21/28 ,  H01L21/768

Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.

公开(公告)号：AU2003279044A1

公开(公告)日：2005-05-11

申请号：AU2003279044

申请日：2003-09-30

Applicant: IBM

Inventor： WALKER GEORGE F ,  VOLANT RICHARD P ,  PETRARCA KEVIN S

IPC: H01R12/00

Abstract: A three-dimensional package consisting of a plurality of folded integrated circuit chips ( 100, 110, 120 ) is described wherein at least one chip provides interconnect pathways for electrical connection to additional chips of the stack, and at least one chip ( 130 ) is provided with additional interconnect wiring to a substrate ( 500 ), package or printed circuit board. Further described, is a method of providing a flexible arrangement of interconnected chips that are folded over into a three-dimensional arrangements to consume less aerial space when mounted on a substrate, second-level package or printed circuit board.