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    CAPACITOR STRUCTURE AND ITS MANUFACTURING METHOD
    32.
    发明专利
    CAPACITOR STRUCTURE AND ITS MANUFACTURING METHOD 失效

    公开(公告)号：JP2001313372A

    公开(公告)日：2001-11-09

    申请号：JP2001090567

    申请日：2001-03-27

    Applicant: IBM

    Inventor： JENNIFER D LYNCH ,  WILBUR D PRISER ,  STAMPER ANTHONY K ,  STEVEN A SAINT ONGE

    IPC: H01L21/28 ,  H01L21/283 ,  H01L21/70 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L27/02 ,  H01L27/04 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To provide a highly reliable chip-on-capacitor. SOLUTION: The capacitor (94) in a semiconductor device (20) has a lower copper plate (30) in a damascene/trench (22), barrier layers (56, 180a) disposed above the lower plate, a dielectric layer (60) disposed above the barrier layers and an upper plate (96) above the dielectric layer. Another embodiment of this invention is capacitors (296, 396) in a semiconductor device, which has two lower plates (230, 231, 330, 331) mutually separated, dielectric layers (260, 360) above the lower plate and upper plates (296, 396) above the dielectric layer which covers the lower plate, extends preferably across it. This invention further includes a method for manufacturing the capacitor of such a constitution.

    METALLIC CAPACITOR AND ITS FORMATION METHOD
    33.
    发明专利
    METALLIC CAPACITOR AND ITS FORMATION METHOD 失效

    公开(公告)号：JP2001313371A

    公开(公告)日：2001-11-09

    申请号：JP2001073042

    申请日：2001-03-14

    Applicant: IBM

    Inventor： ROBERT M JEFFKEN ,  STAMPER ANTHONY K

    IPC: H01L21/3205 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04

    Abstract: PROBLEM TO BE SOLVED: To provide a metallic capacitor which is provided inside a metal layer on a semiconductor chip. SOLUTION: A lower plate of a capacitor is provided between an insulation layer and a dielectric layer. An insulation layer is disposed adjacent to a metallization layer, and a dielectric layer separates a lower plate of a capacitor from the upper plate of the capacitor. The shoulder part of a lower plate is adjacent to it and brought into contact with a via filled with copper. Although a via extends upward to a common surface of the upper plate, it is electrically isolated from an upper plate. A via also extends downward toward a metallization layer. This structure is formed by a copper dual-damascene process.

    STRUCTURE OF PRECISION CIRCUIT ELEMENT AND METHOD OF FORMING IT
    34.
    发明专利
    STRUCTURE OF PRECISION CIRCUIT ELEMENT AND METHOD OF FORMING IT 失效

    公开(公告)号：JP2001308280A

    公开(公告)日：2001-11-02

    申请号：JP2001070049

    申请日：2001-03-13

    Applicant: IBM

    Inventor： STEPHEN H BALDEMAN ,  STAMPER ANTHONY K

    IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L21/822 ,  H01L23/522 ,  H01L23/525 ,  H01L27/04

    Abstract: PROBLEM TO BE SOLVED: To provide a precision circuit element and a method of forming it. SOLUTION: The circuit element is formed as one part of an integrated circuit assembly. The process of the circuit element provides a nominal value of the circuit element that is near to a desired value. An additional trim circuit element is coupled through a link to the nominal circuit element. The Link is a fusible link or an anti fuse. By fusing and cutting the fusible link selectively or by adding or reducing the trim circuit element by fusing the anti fuse, the nominal value of the circuit element is individuated. In a typical example, a capacitor is used.

    CAPACITOR AND FORMING METHOD THEREOF
    35.
    发明专利
    CAPACITOR AND FORMING METHOD THEREOF 失效

    公开(公告)号：JP2001223340A

    公开(公告)日：2001-08-17

    申请号：JP2001014867

    申请日：2001-01-23

    Applicant: IBM

    Inventor： KERRY BERNSTEIN ,  NICHOLAS THEODORE SCHMIDT ,  STAMPER ANTHONY K ,  STEVEN ARTHUR SAINT ONJI ,  STEVEN HOWARD VOLDMAN

    IPC: H01G4/40 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/04

    Abstract: PROBLEM TO BE SOLVED: To provide an interconnecting level capacitor structure and a forming method thereof. SOLUTION: The capacitor structure comprises a first insulating layer disposed on an interconnecting level surface of an integrated circuit, first and second conductors which are formed in the first insulating layer and are isolated by a trench delimited by the first insulating layer, a first conductive barrier layer which is disposed on the first and second conductors and connects the first and second conductors, a second insulting layer disposed on the first conductive barrier layer, a second conductive barrier layer disposed on the second insulating layer, and a third conductor which is disposed in the trench and on the second conductive barrier layer. A capacitance is increased by using regions on a top surface, a bottom surface, and a side surface of the capacitor structure. It is possible to obtain an on-cap decoupling capacitor having a larger size without sacrificing a precious silicon space.

    FORMATION OF COPPER INTERCONNECTION STRUCTURE
    36.
    发明专利
    FORMATION OF COPPER INTERCONNECTION STRUCTURE 失效

    公开(公告)号：JP2000200832A

    公开(公告)日：2000-07-18

    申请号：JP36394999

    申请日：1999-12-22

    Applicant: IBM

    Inventor： PAUL D AGUNERO ,  REENA P BUCKWALTER ,  JOHN HAMEL ,  BARBARA LUTHER ,  STAMPER ANTHONY K

    IPC: H01L23/522 ,  H01L21/04 ,  H01L21/28 ,  H01L21/318 ,  H01L21/768

    Abstract: PROBLEM TO BE SOLVED: To improve adhesiveness of a deposited inorganic barrier film to a copper surface of a copper interconnection structure by including exposure of a copper layer in an interconnected semiconductor structure to a reducing plasma before the formation of the inorganic barrier film on the copper interconnection structure. SOLUTION: A copper interconnection structure is exposed to a reducing plasma before an inorganic barrier film 24 is deposited. This reducing plasma is a non-oxidizing, i.e., oxygen-atom-free plasma atmosphere. A suitable plasma is selected from H2, N2, NH3, and rare gas, but it is not limited to these. Further, a combination of more than two of these reducing plasmas such as N2 and H2 is intended. N2 and NH3 are very preferable among these reducing plasmas. The adhesiveness of the inorganic barrier layer 24 to copper 20 can be improved by using this reducing plasma exposure process.

    MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) AND RELATED ACTUATOR BUMPS, METHOD OF MANUFACTURE AND DESIGN STRUCTURES
    37.
    发明申请
    MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) AND RELATED ACTUATOR BUMPS, METHOD OF MANUFACTURE AND DESIGN STRUCTURES 审中-公开
    微电子机械系统（MEMS）及相关执行机构的制造，制造和设计结构的方法

    公开(公告)号：WO2012177304A3

    公开(公告)日：2014-03-13

    申请号：PCT/US2012029005

    申请日：2012-03-14

    Applicant: IBM ,  JAHNES CHRISTOPHER V ,  STAMPER ANTHONY K

    Inventor： JAHNES CHRISTOPHER V ,  STAMPER ANTHONY K

    IPC: B81B3/00

    CPC classification number: H01H59/0009 ,  B81B3/001 ,  B81B7/0006 ,  B81B2201/016 ,  B81B2203/0118 ,  B81B2203/04 ,  B81C1/0015 ,  B81C1/00293 ,  B81C2203/0145 ,  G06F17/5045 ,  G06F17/5068 ,  H01H1/0036 ,  H01H2001/0057 ,  Y10T29/49121

    Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are provided. The method of forming a MEMS structure includes forming fixed actuator electrodes (115) and a contact point on a substrate. The method further includes forming a MEMS beam (100) over the fixed actuator electrodes and the contact point. The method further includes forming an array of actuator electrodes (105') in alignment with portions of the fixed actuator electrodes, which are sized and dimensioned to prevent the MEMS beam from collapsing on the fixed actuator electrodes after repeating cycling. The array of actuator electrodes are formed in direct contact with at least one of an underside of the MEMS beam and a surface of the fixed actuator electrodes.

    Abstract translation: 提供微机电系统（MEMS）结构，制造方法和设计结构。 形成MEMS结构的方法包括在基板上形成固定的致动器电极（115）和接触点。 该方法还包括在固定的致动器电极和接触点上形成MEMS光束（100）。 该方法还包括形成与固定致动器电极的部分对准的致动器电极阵列（105'），其尺寸和尺寸被设计成防止MEMS梁在重复循环之后塌陷在固定的致动器电极上。 致动器电极的阵列形成为与MEMS光束的下侧和固定的致动器电极的表面中的至少一个直接接触。

    PROTECTION AGAINST CHARGING DAMAGE IN HYBRID ORIENTATION TRANSISTORS
    40.
    发明申请
    PROTECTION AGAINST CHARGING DAMAGE IN HYBRID ORIENTATION TRANSISTORS 审中-公开
    防止混合定向晶体管充电损坏

    公开(公告)号：WO2007115146A3

    公开(公告)日：2008-04-24

    申请号：PCT/US2007065604

    申请日：2007-03-30

    Applicant: IBM ,  HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

    Inventor： HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

    IPC: H02H9/00

    CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207

    Abstract: A chip includes a CMOS structure having a bulk device (20) disposed in a first region (24) of a semiconductor substrate (50) in conductive communication with an underlying bulk region (18) of the substrate, the first region (24) and the bulk region (20) having a first crystal orientation. A SOI device (10) is disposed in a semiconductor-on-insulator ("SOI") layer (14) separated from the bulk region of the substrate by a buried dielectric layer (16), the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor ("PFET") and the SOI device includes an n-type field effect transistor ("NFET") device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor (11) in conductive communication with a gate conductor (21) of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.

    Abstract translation: 芯片包括CMOS结构，该CMOS结构具有布置在半导体衬底（50）的第一区域（24）中的与衬底的下方体区（18）导电连通的体装置（20），第一区域（24）和 该体区域（20）具有第一晶体取向。 SOI器件（10）设置在绝缘体上半导体（“SOI”）层（14）中，所述绝缘体上半导体（SOI）层通过掩埋介电层（16）与衬底的体区分开，SOI层具有与 第一个晶体取向。 在一个示例中，大容量器件包括p型场效应晶体管（“PFET”），并且SOI器件包括n型场效应晶体管（“NFET”）器件。 或者，大容量器件可以包括NFET，并且SOI器件可以包括PFET。 当SOI器件具有与大容量器件的栅极导体（21）导电连通的栅极导体（11）时，除了存在二极管与SOI器件的反向偏置传导通信之外，SOI器件可能会发生充电损坏 地区。 当栅极导体上的电压或SOI器件的源极或漏极区上的电压超过二极管的击穿电压时，二极管可操作以将放电电流传导至体区。

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