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    31.
    发明专利
    未知

    公开(公告)号：DE102004014970B4

    公开(公告)日：2006-12-21

    申请号：DE102004014970

    申请日：2004-03-26

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GREGORIUS PETER

    IPC: H04L7/02 ,  H03L7/081 ,  H03L7/107 ,  H03L7/18 ,  H04L7/00 ,  H04L7/033

    Abstract: The recovery unit has a feed forward phase tracking unit for tracking a sampling time to a center of a unit interval (UI) of a received serial data bit stream. A data recognition unit recovers the received data bit stream. The data recognition unit has parallel data recognition finite impulse response (FIR)-filters connected to a first-in-first-out (FIFO)-register. The FIFO register outputs the recovered data bit stream via an output terminal of the recovery unit. An independent claim is also included for a method for clock and data recovery of a received serial data bit stream.

    33.
    发明专利
    未知

    公开(公告)号：DE102005001892A1

    公开(公告)日：2006-07-27

    申请号：DE102005001892

    申请日：2005-01-14

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： WALLNER PAUL ,  GREGORIUS PETER ,  SCHLEDZ RALF

    IPC: G11C11/4193 ,  G11C7/22 ,  G11C11/4076

    Abstract: The invention relates to a controller for generating control signals (evload_o, odload_o, st_chgclk_o, clk_o , clkorfiford_i) synchronous with a continuous clock signal (clk_hr_i) input to it for a device ( 1 ) to be controlled synchronously with the clock signal (clk_hr_i), wherein the controller (SE) has: register means for registering at least one set signal (st_load_i, st_fiford_i), comprising a plurality of bit positions, counting means for counting edges of the clock signal (clk_hr_i) depending on one or a plurality of set signals respectively registered in the register means, and synchronization and output means for synchronizing a value counted by the counting means with the clock signal (clk_hr_i) and the registered set signal and outputting at least one of the control signals, wherein the register means, the counting means and the synchronization and output means are configured and connected to one another in such a way that the output control signal(s), depending on the respectively registered set signal, occupies (occupy) one of a plurality of temporal positions with a respective phase difference of an integral multiple of half a clock cycle synchronously with the leading or trailing edge of the clock signal. The controller can be applied in particular for controlling the synchronous parallel-serial converter for converting a parallel input signal comprising k bit positions into a serial output signal sequence synchronously with the clock signal (clk_hr_i), which converter is provided in a transmitting circuit in the interface circuit of a very fast DDR DRAM semiconductor memory component of the coming memory generation (e.g. DDR4).

    34.
    发明专利
    未知

    公开(公告)号：DE102005051943A1

    公开(公告)日：2006-07-06

    申请号：DE102005051943

    申请日：2005-10-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GREGORIUS PETER ,  RUCKERBAUER HERMANN ,  SAVIGNAC DOMINIQUE ,  SICHERT CHRISTIAN ,  WALLNER PAUL

    IPC: G11C7/10

    Abstract: The present invention relates to an integrated memory device including: memory cells arranged at wordlines and bitlines, wherein the memory cells are addressable in sets of 2 n bit, wherein n is an integer, a pre-fetch read unit to pre-fetch an addressed set of 2 n data bit in parallel from the addressed memory area, buffer memory to buffer the number of pre-fetched data bits; a number m of output ports to output the data bits buffered in the buffer memory; an output controller for controlling the outputting of the data bits buffered in the buffer memory to the number m of output ports in groups of m bits in one or a plurality of successive cycles, characterized in that the number m of output ports is different to any of the possible numbers 2 n of the sets of addressable memory cells.

    39.
    发明专利
    未知

    公开(公告)号：DE10150536A1

    公开(公告)日：2003-04-30

    申请号：DE10150536

    申请日：2001-10-12

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GREGORIUS PETER ,  HINZ TORSTEN

    IPC: H04L7/00 ,  H04L7/033 ,  H04L25/20

    Abstract: The invention relates to a transceiver, which is configured in particular for transmitting optical data and which contains a device for reconstructing data from a received data signal (RX). Said device comprises a clock pulse recovery unit (3) for recovering a clock pulse of the transmitted data from the received data signal and a data reconstruction unit (2) for reconstructing the transmitted data from the data signal, using the recovered clock pulse (fCLK) and for issuing a data stream (DATA) that is synchronous with the recovered clock pulse. A detector unit (9) identifies an error condition of the received data signal (RX), which prevents a reliable reconstruction of the data. Circuitry comprising a digital phase-locked loop (13) is provided and when an error condition is detected, supplies a signal with a clock pulse, as a reference signal, in place of the received data signal to a phase-locked loop of the clock pulse recovery unit (3). Said replacement signal corresponds to the mean value of the clock pulse (fCLK) that has previously been recovered by the clock pulse recovery unit (3), in such a way that even if an error is detected, the phase-locked loop of the clock pulse recovery unit (3) continues to oscillate in the proper manner.

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