公开(公告)号：JP2006318480A

公开(公告)日：2006-11-24

申请号：JP2006135151

申请日：2006-05-15

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： WALLNER PAUL ,  SCHLEDZ RALF ,  GREGORIUS PETER ,  RUCKERBAUER HERMANN

IPC: G06F12/06 ,  G06F12/00

CPC classification number: G11C5/063

Abstract: PROBLEM TO BE SOLVED: To reduce an entire power consumption as much as possible. SOLUTION: A memory system and method is disclosed. In one embodiment, a memory system has a memory controller and at least one memory module, and the fixed number of semiconductor memory chips and connection lines are disposed in specific connection forms respectively on the memory module. The connection lines have first connection lines. The first connection lines form transmission channels for transmitting data and instruction signal streams on the basis of protocols, from the memory controller to at least one memory chip on the memory module and from memory chips to the memory controller. Second connection lines are independently wired from the memory controller to at least one memory chip on the memory module, for the purpose of directly transmitting selection information to at least one memory chip separately from data and instruction signal streams. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：尽可能减少整体功耗。 解决方案：公开了一种存储器系统和方法。 在一个实施例中，存储器系统具有存储器控制器和至少一个存储器模块，并且固定数量的半导体存储器芯片和连接线分别以特定连接形式设置在存储器模块上。 连接线具有第一连接线。 第一连接线形成用于基于协议从存储器控制器到存储器模块上的至少一个存储器芯片以及从存储器芯片到存储器控制器的传输数据和指令信号流的传输通道。 第二连接线从存储器控制器独立地连接到存储器模块上的至少一个存储器芯片，用于与数据和指令信号流分离地直接将选择信息发送到至少一个存储器芯片。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO02052720A3

公开(公告)日：2003-02-27

申请号：PCT/EP0114288

申请日：2001-12-05

Applicant: INFINEON TECHNOLOGIES AG ,  SCHIMPER MARKUS ,  MECHNIG STEPHAN ,  SCHLEDZ RALF

Inventor： SCHIMPER MARKUS ,  MECHNIG STEPHAN ,  SCHLEDZ RALF

IPC: H03F1/26 ,  H03F3/45

CPC classification number: H03F3/45183 ,  H03F3/45654

Abstract: The invention relates to a circuit for low noise, fully differential amplification. A feedback signal (121) is detected in a differential output step of the differential amplification circuit by means of a voltage distributor formed by a first feedback resistance (119) and a second feedback resistance (120). A first output signal (111) is provided at a first output circuit node (117) and a second output signal (112) is provided at a second output circuit node (118). The respective first and second output signals (111) or (112) form a full output signal which corresponds to an input signal formed by a first and a second input signal (101) or (102). A load current (134), an input current (132) and a reference current (132) are established by means of a load current source (128), an input current source (131) and a reference current source (127). A matching transistor (301) is used to adjust an adaptation between the load current source (128), the input current source (131) and the reference current source (127). A feedback signal (121) of the differential amplification circuit is compared with a reference voltage (122) in a reference step, and the load current (134) is mirrored in the differential input step, in a current mirror device.

Abstract translation: 本发明提供一种低噪声全差分放大，其特征在于，使用第一反馈电阻器（119）和形成的第二反馈电阻电压分配器（120）中的一个的反馈信号（121）设置在所述差动放大器电路的差分输出级确定的电路布置。 的第一输出信号（111）在第一输出节点（117）被提供，而在第二输出节点（118）提供的第二输出信号（112）。 相应的第一和第二输出信号（111）和（112）形成对应于第一和第二输入信号（101）和（102）的输入信号的复合的整体输出信号。 由负载电流源（128）的装置，输入功率源（131）和参考电流源（127）在每种情况下确定的Laststom（134）的输入电流（132）和一个参考电流（133）。 调整晶体管（301）是负载电流源（128），所述Eingangssromquelle（131）和所述参考电流源（127）之间的匹配的设定。 在一个Refernzstufe差分放大器电路的反馈信号（121）与参考电压（122），并在电流镜装置相比，负载电流（134）在所述差分输入级被镜像。

公开(公告)号：WO02052720A8

公开(公告)日：2003-04-10

申请号：PCT/EP0114288

申请日：2001-12-05

Applicant: INFINEON TECHNOLOGIES AG ,  SCHIMPER MARKUS ,  MECHNIG STEPHAN ,  SCHLEDZ RALF

Inventor： SCHIMPER MARKUS ,  MECHNIG STEPHAN ,  SCHLEDZ RALF

IPC: H03F1/26 ,  H03F3/45

CPC classification number: H03F3/45183 ,  H03F3/45654

Abstract: The invention relates to a circuit for low noise, fully differential amplification. A feedback signal (121) is detected in a differential output step of the differential amplification circuit by means of a voltage distributor formed by a first feedback resistance (119) and a second feedback resistance (120). A first output signal (111) is provided at a first output circuit node (117) and a second output signal (112) is provided at a second output circuit node (118). The respective first and second output signals (111) or (112) form a full output signal which corresponds to an input signal formed by a first and a second input signal (101) or (102). A load current (134), an input current (132) and a reference current (132) are established by means of a load current source (128), an input current source (131) and a reference current source (127). A matching transistor (301) is used to adjust an adaptation between the load current source (128), the input current source (131) and the reference current source (127). A feedback signal (121) of the differential amplification circuit is compared with a reference voltage (122) in a reference step, and the load current (134) is mirrored in the differential input step, in a current mirror device.

Abstract translation: 本发明提供一种低噪声全差分放大，其特征在于，使用第一反馈电阻器（119）和形成的第二反馈电阻电压分配器（120）中的一个的反馈信号（121）设置在所述差动放大器电路的差分输出级确定的电路布置。 第一输出节点（111）设置在第一输出节点（117）处，而第二输出（112）设置在第二输出节点（118）处。 相应的第一和第二输出信号（111）和（112）分别形成对应于由第一和第二输入信号（101）和（102）组成的输入信号的总输出信号。 借助负载电流源（128），输入电流源（131）和参考电流源（127）分别确定负载电流（134），输入电流（132）和参考电流（133）。 匹配晶体管（301）用于调整负载电流源（128），输入电流源（131）和参考电流源（127）之间的调整。 在参考级中，差分放大器电路装置的反馈信号（121）与参考电压（122）进行比较，并且在电流镜装置中，负载电流（134）被镜像到差分输入级中。

公开(公告)号：DE102005001892A1

公开(公告)日：2006-07-27

申请号：DE102005001892

申请日：2005-01-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WALLNER PAUL ,  GREGORIUS PETER ,  SCHLEDZ RALF

IPC: G11C11/4193 ,  G11C7/22 ,  G11C11/4076

Abstract: The invention relates to a controller for generating control signals (evload_o, odload_o, st_chgclk_o, clk_o , clkorfiford_i) synchronous with a continuous clock signal (clk_hr_i) input to it for a device ( 1 ) to be controlled synchronously with the clock signal (clk_hr_i), wherein the controller (SE) has: register means for registering at least one set signal (st_load_i, st_fiford_i), comprising a plurality of bit positions, counting means for counting edges of the clock signal (clk_hr_i) depending on one or a plurality of set signals respectively registered in the register means, and synchronization and output means for synchronizing a value counted by the counting means with the clock signal (clk_hr_i) and the registered set signal and outputting at least one of the control signals, wherein the register means, the counting means and the synchronization and output means are configured and connected to one another in such a way that the output control signal(s), depending on the respectively registered set signal, occupies (occupy) one of a plurality of temporal positions with a respective phase difference of an integral multiple of half a clock cycle synchronously with the leading or trailing edge of the clock signal. The controller can be applied in particular for controlling the synchronous parallel-serial converter for converting a parallel input signal comprising k bit positions into a serial output signal sequence synchronously with the clock signal (clk_hr_i), which converter is provided in a transmitting circuit in the interface circuit of a very fast DDR DRAM semiconductor memory component of the coming memory generation (e.g. DDR4).

公开(公告)号：DE10064207A1

公开(公告)日：2002-07-11

申请号：DE10064207

申请日：2000-12-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHIMPER MARKUS ,  MECHNIG SREPHAN ,  SCHLEDZ RALF

IPC: H03F1/26 ,  H03F3/45 ,  H03F1/34

Abstract: The invention relates to a circuit for low noise, fully differential amplification. A feedback signal (121) is detected in a differential output step of the differential amplification circuit by means of a voltage distributor formed by a first feedback resistance (119) and a second feedback resistance (120). A first output signal (111) is provided at a first output circuit node (117) and a second output signal (112) is provided at a second output circuit node (118). The respective first and second output signals (111) or (112) form a full output signal which corresponds to an input signal formed by a first and a second input signal (101) or (102). A load current (134), an input current (132) and a reference current (132) are established by means of a load current source (128), an input current source (131) and a reference current source (127). A matching transistor (301) is used to adjust an adaptation between the load current source (128), the input current source (131) and the reference current source (127). A feedback signal (121) of the differential amplification circuit is compared with a reference voltage (122) in a reference step, and the load current (134) is mirrored in the differential input step, in a current mirror device.

公开(公告)号：DE102011085955B4

公开(公告)日：2020-11-12

申请号：DE102011085955

申请日：2011-11-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUEHN OLAF ,  PRUEGL KLEMENS ,  SCHLEDZ RALF ,  STRASSER ANDREAS DR ,  THYSSEN NORBERT ,  ZIMMER JÜRGEN

IPC: H01L43/08 ,  G01R33/09 ,  H01L27/22 ,  H01L43/12

Abstract: Magnetoresistives Sensorelement, das folgende Merkmale aufweist:einen ersten magnetoresistiven Stapelabschnitt (103), der eine freie Schicht (104) aufweist und eine erste, eine zweite, eine dritte und eine vierte Seite aufweist; undeinen zweiten magnetoresistiven Stapelabschnitt (111), der auf den ersten magnetoresistiven Stapelabschnitt (103) aufgebracht ist und der eine fünfte, eine sechste, eine siebte und eine achte Seite aufweist, von denen jede mit der ersten, der zweiten, der dritten und der vierten Seite nicht bündig abschließt;wobei der erste magnetoresistive Stapelabschnitt (103) anhand eines Damaszener-Prozesses gebildet ist,wobei der zweite magnetoresistive Stapelabschnitt (111) anhand eines Ätzprozesses strukturiert ist,wobei laterale Abmessungen des zweiten magnetoresistiven Stapelabschnitts (111) größer sind als laterale Abmessungen des ersten magnetoresistiven Stapelabschnitts (103).

公开(公告)号：DE102005001894A1

公开(公告)日：2006-08-03

申请号：DE102005001894

申请日：2005-01-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WALLNER PAUL ,  GREGORIUS PETER ,  SCHLEDZ RALF

IPC: H03M9/00 ,  G11C19/00

Abstract: The synchronous parallel-series converter has first shift register (SRod) which accepts odd-numbered part (D1od(1/8)) of input signal synchronously to rear and front flank of the clock pulse (clkhri) with a first load signal (odloadi) and lets it serially pass as first one-bit signal sequence (D2od(1/2)). A second shift register (SRev) accepts an even-numbered part (D1ev(1/8)) of input signal synchronously to front or rear flank of the clock pulse with a second load signal (evloadi) and lets it serially pass as a second one-bit signal sequence (D2ev(1/2)). A fusion unit (M) accepts the first one-bit signal sequence from first shift register and second one-bit signal sequence from the second shift register. The clock pulse and the first one-bit signal sequence merges synchronously with the rear or front flank of the clock pulse. The second one-bit signal sequence merges synchronously with the front or rear flank of the clock pulse to output signal (D3(1/1)). An independent claim is also included for the use of the synchronous parallel-series converter.

公开(公告)号：DE50209650D1

公开(公告)日：2007-04-19

申请号：DE50209650

申请日：2002-04-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BACHHUBER MARCO ,  SCHLEDZ RALF

IPC: H03M1/68 ,  H03M1/76

Abstract: The device has 2 to the power of b digital to analog converters, where b is an integer greater than 0 and each converter converts a digital value containing a-b bits, where a is the number of bits in the value to be converted. The value fed to the a converter corresponds to the a-b most significant bits of the sum of the value to be converted and to a value given by a stated relationship.

公开(公告)号：DE102006031055A1

公开(公告)日：2007-02-01

申请号：DE102006031055

申请日：2006-07-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUCKERBAUER HERMANN ,  SAVIGNAC DOMINIQUE ,  SCHLEDZ RALF ,  SICHERT CHRISTIAN ,  FUKUZO YUKIO

IPC: G11C7/10 ,  G11C29/24 ,  G11C29/52

Abstract: The device has a memory cell operated in a mode, in which the cell is directly operated as a memory device for error-correcting code (ECC)-information. The cell is operated in another mode, in which the cell serves as the memory device for storing information, which is different from the ECC -information. A signal control device (CTRL) is used for signaling in such a manner that the cell is operated in the former or latter mode. An independent claim is also included for a method for operating a semiconductor memory device.

公开(公告)号：DE10345521B3

公开(公告)日：2005-08-25

申请号：DE10345521

申请日：2003-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLEIN AXEL ,  AUGUSTYNIAK MARCIN ,  SCHLEDZ RALF

IPC: H03F1/08 ,  H03F1/14 ,  H03F1/34 ,  H03F3/30 ,  H03F3/45

Abstract: The invention provides an amplifier arrangement which is of multistage design. The output transistor in the output stage has a coupling path between its control input and its controlled path. The coupling path comprises a series circuit comprising a Miller compensation capacitance and a resistance with a controllable resistance value. It is thus possible to ensure stable operation of the amplifier regardless of bias and load conditions while simultaneously reducing the quiescent current drawn.