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    31.
    发明专利
    未知

    公开(公告)号：DE502006004698D1

    公开(公告)日：2009-10-15

    申请号：DE502006004698

    申请日：2006-02-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GUTSCHE MARTIN ,  SEIDL HARALD

    IPC: H01L21/308 ,  H01L21/033

    Abstract: The method involves preparing substrate (1), forming first auxiliary layer and then second auxiliary layer structure (3,4). The first auxiliary layer is anisotropically etched using the auxiliary structure as a mask to form an anisotropic structured first auxiliary layer structure. This is reverse isotropically etched to remove sections and form an isotropically structured first auxiliary structure. A mask is formed over the sections. This is anisotropically etched to the substrate to form sublithographic structure (5A). Auxiliary structures are removed to reveal the sublithographic structure.

    32.
    发明专利
    未知

    公开(公告)号：DE10337858B4

    公开(公告)日：2007-04-05

    申请号：DE10337858

    申请日：2003-08-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SEIDL HARALD ,  SAENGER ANNETTE ,  KUDELKA STEPHAN ,  GUTSCHE MARTIN

    IPC: H01L21/8242 ,  H01L21/02 ,  H01L21/334 ,  H01L27/108 ,  H01L29/94

    Abstract: Production of a trench capacitor (1) in a semiconductor substrate (10) comprises providing a separating layer (6) on a dielectric layer (5) and forming an inner electrode (3) made from a metal or metal compound and extending over a collar region (12) and active region (13). Independent claims are also included for the following: (1) Trench capacitor produced by the above process; (2) Memory cell containing the trench capacitor; and (3) Memory arrangement containing the memory cell.

    33.
    发明专利
    未知

    公开(公告)号：DE10308888B4

    公开(公告)日：2006-12-28

    申请号：DE10308888

    申请日：2003-02-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GUTSCHE MARTIN ,  SEIDL HARALD

    IPC: H01L27/108 ,  H01G4/228 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94

    Abstract: An arrangement of at least two capacitors (14,15) in or on a substrate (2), where outer capacitor (14) at least partially encloses inner capacitor (15). An independent claim is included for a process of preparing the arrangement in which a trough (16) is introduced into prepared substrate (2), a first dielectric layer (17) is formed on the trough wall, a first electrode layer (18) is applied to layer (17), a second dielectric layer (20) to layer (18), and contact layers and further dielectric and electrode layers are then applied.

    37.
    发明专利
    未知

    公开(公告)号：DE102004042174A1

    公开(公告)日：2006-03-02

    申请号：DE102004042174

    申请日：2004-08-31

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BRUCHHAUS RAINER ,  GUTSCHE MARTIN ,  PINNOW CAY-UWE

    IPC: G11C11/22 ,  H01L21/316 ,  H01L27/105

    Abstract: A ferroelectric memory arrangement having memory cells, in each of which a vertical ferroelectric storage capacitor, which includes vertical electrodes and a ferroelectric dielectric between the vertical electrodes, is connected to a select transistor, the ferroelectric dielectric a plurality of ferroelectric layers, between each of which is arranged an insulating separating layer.

    38.
    发明专利
    未知

    公开(公告)号：DE69826934T2

    公开(公告)日：2005-10-13

    申请号：DE69826934

    申请日：1998-06-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GUTSCHE MARTIN ,  TOBBEN DIRK

    IPC: H01L21/28 ,  H01L21/768

    Abstract: A method for manufacturing a dual damascene structure includes the use of a sacrificial stud (12) and provides an improved defined edge on the interface between the conductive line openings (9) and the via openings (11).

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