公开(公告)号：DE10120929A1

公开(公告)日：2002-10-31

申请号：DE10120929

申请日：2001-04-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KROENKE MATTHIAS ,  WANG KAE-HORNG ,  GUSTIN WOLFGANG

IPC: H01L21/283 ,  H01L21/302 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L27/11521

Abstract: The invention relates to a method for the production of an integrated circuit, comprising the following steps: a substrate (1) is provided with at least one first, second and third gate stack (GS1, GS2, GS3) of approximately the same height on the surface of said substrate, a common active area (60) being provided on the surface of the substrate in said substrate (1) between the first and second gate stack (GS1, GS2); a first insulating layer (70) is provided in order to cover the embedding of the first, second and third gate stack (GS1, GS2, GS3); the upper side of a gate connection (20) of the third gate stack (GS3) is uncovered; a second insulating layer (80) is provided in order to cover the upper side of a gate connection (20); a mask (M2) is provided on the resulting structure having a first opening (F2a) above the uncovered upper side of the gate connection (20) of the third gate stack (GS3), a second opening (F2b) above the substrate (1) between the third and second gate stack (GS3, GS2) and a third opening (F2c) above the common active area (60), partially overlapping the first and second gate stack (GS1, GS2), and simultaneously forming a first, second and third contact hole (KB, KS, KG) using said mask (32) in an etching process, the first contact hole (KB) uncovering the common active area (60) on the surface of the substrate between the first and second gate stack (GS1, GS2), the second contact hole (KS) uncovering the surface of the substrate between the second and third gate stack (GS2, GS2) and the third contact hole (KG) uncovering the upper side of the gate connection (20) of the third gate stack (GS3).

公开(公告)号：DE10105673A1

公开(公告)日：2002-09-05

申请号：DE10105673

申请日：2001-02-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KASKO IGOR ,  HARTNER WALTER ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/8239

Abstract: Production of a stacked integrated ferroelectric semiconductor storage device or a DRAM cell comprises depositing an oxygen barrier (3) between a capacitor electrode (4) and an electrically conducting plug (1) which connects the electrode to a semiconductor electrode; and carrying out a rapid thermal processing step at 700-1000 deg C, preferably 800-900 deg C, after depositing the ferroelectric or high iota -material dielectric but before tempering. An Independent claim is also included for an integrated DRAM cell produced. Preferred Features: The temperature of the tempering step is below the temperature of the rapid thermal processing step. The oxygen barrier is made from Ir/IrOx.

公开(公告)号：DE10105997C1

公开(公告)日：2002-07-25

申请号：DE10105997

申请日：2001-02-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KASKO IGOR ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS

IPC: H01L27/105 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507 ,  H01L21/8239

Abstract: Production of a ferroelectric capacitor in integrated semiconductor storage chips comprises forming an adhesion layer (3) unstructured in a region containing ferroelectric capacitors (10, 11) between a conducting plug (1a, 1b) and an oxygen barrier (4a, 4b); exposing the adhesion layer in sections by oxidizing using the oxygen barrier; and converting into an insulating layer. Preferably the adhesion layer contains tantalum. The conducting plug is made from polysilicon or tungsten. The oxidized sections extend below the edge regions of the oxygen barrier.

公开(公告)号：DE10131492B4

公开(公告)日：2006-09-14

申请号：DE10131492

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L21/8239 ,  G11C7/00 ,  H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507

公开(公告)号：DE102004020938B3

公开(公告)日：2005-09-08

申请号：DE102004020938

申请日：2004-04-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KROENKE MATTHIAS ,  PATZER JOACHIM ,  GRAF WERNER

IPC: H01L21/283 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242

Abstract: Producing a primary contact hole plane in a storage building block, comprises preparing a semiconductor substrate with a cell region (20) and a logic region (30), which have adjacent gate electrode sections (21,31) on the semiconductor surface (10). Gate electrode sections have a silicon dioxide cover layer, and an insulating layer (11) is located between them. A silicon dioxide layer (12) in formed on the insulation. A primary mask is applied which is then structured and etched near the gate contact. The mask is then removed and a sacrificial layer is formed followed by a secondary mask. The latter is structured to establish contact openings, which are then etched. The secondary mask is removed and a filling layer is applied between sacrificial layer blocks. The blocks are then removed and the gate electrode and semiconductor surfaces are anisotropically etched.

公开(公告)号：DE10326319B3

公开(公告)日：2004-12-16

申请号：DE10326319

申请日：2003-06-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PATZER JOACHIM ,  KROENKE MATTHIAS

IPC: H01L21/283 ,  H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242

Abstract: Production of an electrical contact in an integrated circuit comprises applying and structuring a hard mask layer (8) on an insulating layer (6,7) to form regions for contact hole openings in the insulating layer to contact the components formed in a silicon wafer (1) for subsequent anisotropic etching, and completely removing the hard mask layer from the insulating layer after inserting a filler layer (10) in the contact hole openings.

公开(公告)号：DE10131627A1

公开(公告)日：2003-01-30

申请号：DE10131627

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507 ,  H01L21/8239 ,  H01L27/105

Abstract: Semiconductor memory has capacitor devices (10-1,...., 10-4) each vertically extending from a substrate (20) and/or a passivating region (21) and/or a surface region (20a). A three dimensional arrangement or structure is formed for each capacitor device. An Independent claim is also included for a process for the production of a semiconductor memory. Preferred Features: The capacitor devices each have a first electrode arrangement (14), a second electrode arrangement (18) with a dielectric (16) arranged between the arrangements. The capacitor devices are a stacked structure of form part of a stacked structure.

公开(公告)号：DE10131624A1

公开(公告)日：2003-01-23

申请号：DE10131624

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/105 ,  H01L21/8239

Abstract: A method for manufacturing a semiconductor memory device, in which a semiconductor substrate (20) a passivation zone (21) and/or a surface zone (20a, 21a) are designed with a CMOS structure. The capacitor device (10-1...10-4) is structured mainly in the horizontally-extending semiconductor substrate or similar of a passivation zone (21) and/or a surface zone from it, at least partly and/or locally structured and mainly vertically formed. A passivation zone (21) and/or a surface zone (20a, 21a) is formed and/or structured at least partly in the arrangement or structure extending in the third dimension for the respective capacitor device (10-1...10-4). An Independent claim is given for a chain-FeRAM store. (B)

公开(公告)号：DE10131492A1

公开(公告)日：2003-01-16

申请号：DE10131492

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: G11C7/00 ,  H01L21/02 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507

Abstract: Production of a semiconductor device comprises forming and/or structuring capacitor arrangements (10-1, ..., 10-4) on a semiconductor substrate (20), a passivating region (21) and/or surface region (20a, 21a), and forming a three-dimensional arrangement for the capacitor arrangements. An Independent claim is also included for the semiconductor device produced by the above process. Preferred Features: Electrode arrangements (14, 18) and a dielectric (16) of each capacitor arrangement are formed and/or structured on the substrate, passivating region and/or surface region.

公开(公告)号：DE10112276A1

公开(公告)日：2002-10-02

申请号：DE10112276

申请日：2001-03-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KROENKE MATTHIAS ,  KASKO IGOR ,  WEINRICH VOLKER

IPC: H01L21/02 ,  H01L21/285 ,  H01L27/115 ,  H01L27/11502 ,  H01L21/8239 ,  H01L27/105

Abstract: The integrated ferroelectric semiconductor memory is fabricated according to the stack cell principle. A ferroelectric capacitor module is formed on an intermediate oxide above a selection transistor located in or on a semiconductor wafer. The capacitor module is brought into conductive contact by its bottom capacitor electrode with an electrode of the selection transistor by means of an electrically conductive plug leading through the intermediate oxide. A layer system of a conductive oxygen diffusion barrier and a conductive adhesion layer is deposited directly below the bottom capacitor electrode, and the adhesion layer and the overlying oxygen diffusion barrier are deposited directly into the contact hole and form the plug at least in the region lying directly below the bottom capacitor electrode.