公开(公告)号：DE102005001291A1

公开(公告)日：2006-07-06

申请号：DE102005001291

申请日：2005-01-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKSCHIK STEFAN ,  MIKOLAJICK THOMAS ,  GOLDBACH MATTHIAS ,  HECHT THOMAS

IPC: H01L27/115 ,  H01L21/8247

公开(公告)号：DE10065664B4

公开(公告)日：2005-07-28

申请号：DE10065664

申请日：2000-12-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MIKOLAJICK THOMAS ,  KASTNER MARCUS J

IPC: H01L21/02 ,  H01L27/06 ,  H01L27/108 ,  H01L27/12

Abstract: The integrated ferroelectric or DRAM semiconductor memory configuration has memory cells each with a selection transistor and a capacitor module that can be addressed by the selection transistor. The capacitors of successive memory cells are formed alternately on the front and rear sides of a substrate wafer.

公开(公告)号：DE10333557A1

公开(公告)日：2005-02-24

申请号：DE10333557

申请日：2003-07-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUND MICHAEL ,  MIKOLAJICK THOMAS ,  PINNOW CAY-UWE

IPC: G11C13/02 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/792 ,  H01L21/8247 ,  H01L21/8239 ,  H01L51/20

Abstract: When fabricating a memory cell with an organic storage layer which stores a digital information item, processing of polycrystalline and monocrystalline semiconductor structures in which high temperatures are employed is concluded prior to application of the organic storage layer.

公开(公告)号：DE10323414A1

公开(公告)日：2004-12-23

申请号：DE10323414

申请日：2003-05-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PINNOW CAY-UWE ,  MIKOLAJICK THOMAS ,  HAPP THOMAS ,  SYMANCZYK RALF

IPC: G11C11/34 ,  G11C13/02 ,  H01L45/00

Abstract: A solid-state electrolyte memory cell comprises a memory region (S) between anode (A) and cathode (K) on an ion-conductive material (I) having regions of different and controllable variable conductance (G). A barrier layer (B) between the ion-conductive and cathode layers suppresses a short, low-resistance error or hard write condition.

公开(公告)号：DE10250357A1

公开(公告)日：2004-05-19

申请号：DE10250357

申请日：2002-10-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PINNOW CAY-UWE ,  MIKOLAJICK THOMAS ,  MOERT MANFRED

IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/115 ,  G11C11/36 ,  G11C11/40

公开(公告)号：DE10153493A1

公开(公告)日：2003-05-15

申请号：DE10153493

申请日：2001-10-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MIKOLAJICK THOMAS

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/423 ,  H01L29/788

Abstract: The memory cell has a source/drain configuration accessing a floating gate configuration, having floating gates each for storing information. A control gate configuration having multiple control gates controls the access to each floating gate. The source/drain configuration having two source/drain regions permits the access of all floating gates through two common source/drain regions. An Independent claim is also included for the method for fabricating floating gate configuration.

公开(公告)号：DE10153384A1

公开(公告)日：2003-05-15

申请号：DE10153384

申请日：2001-10-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MIKOLAJICK THOMAS

IPC: G11C16/04 ,  H01L21/28 ,  H01L29/788 ,  H01L29/792

Abstract: A memory gate configuration has several gate regions (F1,F2) that are spatially separated from each other by an insulation region (110). Independent claims are also included for the following: (1) semiconductor memory device; and (2) method for fabricating semiconductor memory cell.

公开(公告)号：DE102006017282A1

公开(公告)日：2007-10-04

申请号：DE102006017282

申请日：2006-04-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NAGEL NICOLAS ,  KUESTERS KARL-HEINZ ,  WILLER JOSEF ,  MIKOLAJICK THOMAS

IPC: H01L27/115 ,  G11C16/04

Abstract: The method involves changing threshold voltage of a charge-trapping-unit that includes a channel region (2), gate electrode (3), and a charge-trapping-layer (4) between the channel region and the electrode. Voltage is applied between the electrode and the channel region. Current of two sets of charge carriers is respectively generated from the channel region and the electrode in the charge-trapping layer. The current generation is stopped, if the amount of current intensity of one carrier is larger than the amount of the current intensity of the other carrier. An independent claim is also included for a semiconductor memory unit with a channel region and a gate electrode.

公开(公告)号：DE10153384B4

公开(公告)日：2007-08-02

申请号：DE10153384

申请日：2001-10-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MIKOLAJICK THOMAS

IPC: G11C16/04 ,  H01L21/28 ,  H01L29/788 ,  H01L29/792

Abstract: A memory gate configuration has several gate regions (F1,F2) that are spatially separated from each other by an insulation region (110). Independent claims are also included for the following: (1) semiconductor memory device; and (2) method for fabricating semiconductor memory cell.

公开(公告)号：DE10326805B4

公开(公告)日：2007-02-15

申请号：DE10326805

申请日：2003-06-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  MIKOLAJICK THOMAS ,  BIRNER ALBERT

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/788

Abstract: Silicon nanocrystals are applied as storage layer ( 6 ) and removed using spacer elements ( 11 ) laterally with respect to the gate electrode ( 5 ). By means of an implantation of dopant, source/drain regions ( 2 ) are fabricated in a self-aligned manner with respect to the storage layer ( 6 ). The portions of the storage layer ( 6 ) are interrupted by the gate electrode ( 5 ) and the gate dielectric ( 4 ), so that a central portion of the channel region ( 3 ) is not covered by the storage layer ( 6 ). This memory cell is suitable as a multi-bit flash memory cell in a virtual ground architecture.