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    31.
    发明专利
    未知

    公开(公告)号：AT367609T

    公开(公告)日：2007-08-15

    申请号：AT00965852

    申请日：2000-09-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SEDLAK HOLGER ,  KNIFFLER OLIVER ,  GAERTNER WOLFGANG

    IPC: G06F13/362

    Abstract: A method of operating a processor bus, with which a central unit (processor) makes accesses to various peripheral units, is described. The processor bus has the ability to change the order of the accesses as a function of the operating state of the peripheral units, and the peripheral units can either reject or delay the access.

    34.
    发明专利
    未知

    公开(公告)号：AT357016T

    公开(公告)日：2007-04-15

    申请号：AT02714108

    申请日：2002-01-24

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ELBE ASTRID ,  SEDLAK HOLGER ,  JANSSEN NORBERT ,  SEIFERT JEAN-PIERRE

    IPC: G06F7/72

    Abstract: A multiplicand is multiplied by a multiplier using a modulus. The multiplicand, the multiplier and the modulus are polynomials of variable. A multiplication look-ahead method to obtain a multiplication shift value is carried out. An intermediate result polynomial is shifted to the left by the number of digits of the multiplication shift value. A reduction shift value equalling the difference of the degree of the shifted intermediate result polynomial and the degree of the modulus polynomial is obtained in a reduction look-ahead method. The modulus polynomial is then shifted by a number of digits equalling the reduction shift value. In a three-operands addition, the shifted polynomial and the multiplicand are summed and the shifted modulus polynomial is subtracted. The modular multiplication are iteratively executed and processed progressively until all the powers of the multiplier polynomial have been processed. With a carry disabling function Z/NZ arithmetic and GF arithmetic can be carried out on a single long number calculating unit.

    37.
    发明专利
    未知

    公开(公告)号：FR2855626B1

    公开(公告)日：2006-12-01

    申请号：FR0405277

    申请日：2004-05-14

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SEDLAK HOLGER ,  KUNEMUND THOMAS

    IPC: G06F9/30 ,  G06F21/75 ,  G11C11/41 ,  G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  G11C11/413

    Abstract: An integrated circuit having at least one line pair to which a dual-rail signal is applied, a switching device, which is connected to the at least one line pair, is controlled by a signal applied to a control connection and is used to transmit the dual-rail signal, which has been applied to the line pair, to an additional line pair, and a memory cell, which is connected to the additional line pair and to a supply potential connection via a controllable switch.

    38.
    发明专利
    未知

    公开(公告)号：DE50206838D1

    公开(公告)日：2006-06-22

    申请号：DE50206838

    申请日：2002-10-31

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GAMMEL M ,  KUENEMUND THOMAS ,  SEDLAK HOLGER

    IPC: G06F12/14 ,  G06F1/00 ,  G06F12/0804 ,  G06F21/24 ,  H04L9/10

    Abstract: Method for synchronizing a cache memory with a main memory, the cache memory provided to buffer-store data between a processor and the main memory, and memory entries of the cache memory each having a data area and an identification area. The processor provides a synchronization value to determine which memory entries of the data area are to be synchronized with the main memory. A cache logic circuit of the cache memory then compares the synchronization value with contents of a memory field of each memory entry. When there is a match, the cache logic circuit checks a flag of a third memory field of the identification area for a first state, which indicates that a change was made to the data area of the memory entry since the last synchronization. When the flag is in the first state, the contents of the data area are transferred to the main memory.

    39.
    发明专利
    未知

    公开(公告)号：DE59813069D1

    公开(公告)日：2006-02-02

    申请号：DE59813069

    申请日：1998-07-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SEDLAK HOLGER

    IPC: G09C1/00 ,  G07F7/10 ,  H04L9/32

    Abstract: A device for reliably creating electronic signatures that includes a data carrier read/write device, a data generating device, and a display device. The data carrier read/write device is for receiving a portable data carrier storing a user-specific key and an algorithm used to generate an electronic signature. The data generating device is connected to the data carrier read/write device for transmitting data to the data carrier read/write device. The display device is connected to the data generating device to display the data that has been transmitted to the data carrier read/write device. The data carrier read/write device includes an actuating element operatively connected to the data carrier read/write device and operatively connected to the portable data carrier when the portable data carrier is received by the data carrier read/write device. The data carrier read/write device is configured to encrypt the data that has been transmitted to the data carrier read/write device to form the electronic signature only when the actuating element is actuated by a user.

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