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    31.
    发明专利
    未知

    公开(公告)号：DE10157280A1

    公开(公告)日：2003-06-12

    申请号：DE10157280

    申请日：2001-11-22

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MEYER THORSTEN ,  FRANKOWSKY GERD ,  HEDLER HARRY ,  IRSIGLER ROLAND ,  VASQUEZ BARBARA

    IPC: H01L21/00 ,  H01L21/60 ,  H01L21/78 ,  H01L21/56

    Abstract: The invention creates a method for connection of circuit units (101a-10n) which are arranged on a wafer (100), in which the wafer (100) is fitted to a first film (102a), the wafer (100) is sawn such that the circuit units (101a-101n) which are arranged on the wafer (100) are separated, the functional circuit units (101d) are picked up by means of a handling device (101) and are placed down on a second film (102b) by means of the handling device (103), so as to produce a separation distance which can be predetermined between connection contacts of the circuit units (101d).

    33.
    发明专利
    未知

    公开(公告)号：DE10123686C1

    公开(公告)日：2003-03-20

    申请号：DE10123686

    申请日：2001-05-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HEDLER HARRY ,  IRSIGLER ROLAND ,  VASQUEZ BARBARA

    IPC: H01L21/66 ,  H01L23/525 ,  H01L21/768

    Abstract: A method for producing an electronic component, especially a memory chip, using a laser-induced correction to equalize an integrated circuit by means of at least one laser via in a layer at least partially covering the circuit. The component comprises a rewiring of the contact pads. The inventive method comprises the following steps: each laser via is closed by means of a separate covering layer which is to be applied locally; a rewiring extending between the local covering layers is created; the local covering layers are removed; and the laser-induced correction is carried out by means of the open laser vias.

    35.
    发明专利
    未知

    公开(公告)号：DE60035994D1

    公开(公告)日：2007-09-27

    申请号：DE60035994

    申请日：2000-10-04

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： VASQUEZ BARBARA

    IPC: H01L21/768 ,  H01L21/78 ,  H01L21/98 ,  H01L25/065

    Abstract: In the method an SOI wafer having fully processed devices in its uppermost Si layer is reduced in thickness from a surface opposite to the device layer surface by performing a first etching step of etching the semiconductor substrate (1) to the insulation layer (2), so that the insulation layer (2) functions as an etch stop layer, and a second etching step of etching the insulation layer (2) to the semiconductor device layer (3), so that the semiconductor device layer (3) functions as an etch stop layer. The semiconductor device layer is then separated into individual chips for fabricating a three-dimensionally integrated circuit thereof.

    39.
    发明专利
    未知

    公开(公告)号：DE10202881A1

    公开(公告)日：2003-08-14

    申请号：DE10202881

    申请日：2002-01-25

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： IRSIGLER ROLAND ,  HEDLER HARRY ,  VASQUEZ BARBARA

    IPC: H01L21/301 ,  H01L21/304 ,  H01L21/44 ,  H01L21/46 ,  H01L21/48 ,  H01L21/50 ,  H01L21/78 ,  H01L23/00

    Abstract: The present invention provides a method of producing semiconductor chips (1a, 1b, 1c; 1a', 1b', 1c') with a protective chip-edge layer (21'', 22''), in particular for wafer level packaging chips, with the steps of: preparing a semiconductor wafer (1); providing trenches (21, 22) in the semiconductor wafer to establish chip edges on a first side of the semiconductor wafer (1); filling the trenches (21, 22) with a protective agent (21'; 22'); grinding back the semiconductor wafer (1) from a second side of the semiconductor wafer (1), which is opposite from the first side, to expose the trenches (21, 22) filled with the protective agent (21'; 22'); and cutting through the trenches (21, 22) filled with the protective agent (21'; 22'), so that the protective chip-edge layer (21'', 22'') comprising the protective agent (21', 22') remains on the chip edges.

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