公开(公告)号：DE10216614A1

公开(公告)日：2003-10-30

申请号：DE10216614

申请日：2002-04-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HECHT THOMAS ,  BIRNER ALBERT ,  SEIDL HARALD ,  SCHROEDER UWE ,  JAKSCHIK STEFAN ,  GUTSCHE MARTIN

IPC: C25D11/02 ,  C25D11/32 ,  H01L21/316 ,  H01L21/8242 ,  H01G9/04

Abstract: Production of a thin dielectric layer (2) on a conducting substrate (1) comprises applying a thin dielectric layer on the substrate, placing in an electrochemical cell (5) filled with an electrolyte (9) and having two electrodes (6, 7), connecting the substrate with the first electrode and the second electrode with the electrolyte, and applying an electrical potential between the electrodes. The current flow between the electrolyte and substrate is controlled in an electrochemical process and is adjusted by the dielectric layer, preferably in the region of defect sites. An Independent claim is also included for an arrangement of a substrate and a dielectric layer.

公开(公告)号：DE10217261A1

公开(公告)日：2003-08-07

申请号：DE10217261

申请日：2002-04-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  GUTSCHE MARTIN ,  POPP MARTIN ,  SEIDL HARALD

IPC: H01L21/8242 ,  H01L27/108

公开(公告)号：DE10136400A1

公开(公告)日：2003-02-27

申请号：DE10136400

申请日：2001-07-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  SAENGER ANNETTE ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  MOLL PETER

IPC: C23C16/32 ,  C23C16/44 ,  C23C16/455 ,  C23C16/56 ,  H01L21/285 ,  H01L21/8242 ,  H01L27/108

Abstract: At least a partial layer of an upper capacitor electrode is formed by metal carbide, preferably by a transition metal carbide. In one embodiment, the metal carbide layer is formed by depositing an alternating sequence of metal-containing layers and carbon-containing layers on top of one another and then subjecting them to a heat treatment, in such a manner that they mix with one another. The patterning of the layer sequence can be carried out before the carbide formation step.

公开(公告)号：DE502006004698D1

公开(公告)日：2009-10-15

申请号：DE502006004698

申请日：2006-02-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GUTSCHE MARTIN ,  SEIDL HARALD

IPC: H01L21/308 ,  H01L21/033

Abstract: The method involves preparing substrate (1), forming first auxiliary layer and then second auxiliary layer structure (3,4). The first auxiliary layer is anisotropically etched using the auxiliary structure as a mask to form an anisotropic structured first auxiliary layer structure. This is reverse isotropically etched to remove sections and form an isotropically structured first auxiliary structure. A mask is formed over the sections. This is anisotropically etched to the substrate to form sublithographic structure (5A). Auxiliary structures are removed to reveal the sublithographic structure.

公开(公告)号：DE102005016925B4

公开(公告)日：2008-09-04

申请号：DE102005016925

申请日：2005-04-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  GUTSCHE MARTIN ULRICH

IPC: H01L21/336

公开(公告)号：DE10337858B4

公开(公告)日：2007-04-05

申请号：DE10337858

申请日：2003-08-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  SAENGER ANNETTE ,  KUDELKA STEPHAN ,  GUTSCHE MARTIN

IPC: H01L21/8242 ,  H01L21/02 ,  H01L21/334 ,  H01L27/108 ,  H01L29/94

Abstract: Production of a trench capacitor (1) in a semiconductor substrate (10) comprises providing a separating layer (6) on a dielectric layer (5) and forming an inner electrode (3) made from a metal or metal compound and extending over a collar region (12) and active region (13). Independent claims are also included for the following: (1) Trench capacitor produced by the above process; (2) Memory cell containing the trench capacitor; and (3) Memory arrangement containing the memory cell.

公开(公告)号：DE10308888B4

公开(公告)日：2006-12-28

申请号：DE10308888

申请日：2003-02-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GUTSCHE MARTIN ,  SEIDL HARALD

IPC: H01L27/108 ,  H01G4/228 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94

Abstract: An arrangement of at least two capacitors (14,15) in or on a substrate (2), where outer capacitor (14) at least partially encloses inner capacitor (15). An independent claim is included for a process of preparing the arrangement in which a trough (16) is introduced into prepared substrate (2), a first dielectric layer (17) is formed on the trough wall, a first electrode layer (18) is applied to layer (17), a second dielectric layer (20) to layer (18), and contact layers and further dielectric and electrode layers are then applied.

公开(公告)号：DE102005022017B3

公开(公告)日：2006-10-26

申请号：DE102005022017

申请日：2005-05-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTH HANS-JOACHIM ,  SEIDL HARALD

IPC: H01L21/58 ,  H01L21/301 ,  H01L25/04

Abstract: The method involves superimposing isolated (CH2) and non-isolated semiconductor chips on a connection layer. An intermediate space between the isolated chips is filled with a stabilization layer. A wafer with the non-isolated chips is thinned and sawed to manufacture an isolated chip stack. The layer is held at a chemical mechanical polishing (CMP)- or etched stop layer (4B) during the thinning process. An independent claim is also included for a chip stack with two sets of semiconductor chips.

公开(公告)号：DE10142580B4

公开(公告)日：2006-07-13

申请号：DE10142580

申请日：2001-08-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  GUTSCHE MARTIN ,  HECHT THOMAS ,  LEONHARDT MATTHIAS ,  SCHROEDER UWE

IPC: H01L21/8242

公开(公告)号：DE102004012855B4

公开(公告)日：2006-02-02

申请号：DE102004012855

申请日：2004-03-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: The present invention provides a trench capacitor, in particular for use in a semiconductor memory cell, having a trench ( 5 ) formed in a semiconductor substrate ( 1 ); an insulation collar ( 3 ) in the upper region of the trench ( 5 ); a first conductive capacitor electrode ( 1 a) situated in the trench ( 5 ) or in the semiconductor substrate ( 1 ); a conductive second capacitor electrode ( 10, 25, 30 ), situated in the trench ( 5 ), has a lower nonmetallic part ( 10 ) and an upper metallic part ( 30 ), the upper metallic part ( 30 ) extending right into the region between the insulation collar ( 3 ); a dielectric layer ( 4 ) as capacitor dielectric situated between the first and second capacitor electrodes ( 1 a; 10, 25, 30 ). A part ( 25 ) made of a metal silicide is situated between the lower nonmetallic part ( 10 ) and the upper metallic part ( 30 ). The invention likewise provides a corresponding fabrication method.