公开(公告)号：WO1981001684A1

公开(公告)日：1981-06-25

申请号：PCT/US1980001593

申请日：1980-11-28

Applicant: NCR CORP

Inventor： NCR CORP ,  LAWTER R ,  SAMPSON E ,  WILLS D ,  BRIGGS B

IPC: B41J01/08

CPC classification number: B41J27/02 ,  B41J1/12

Abstract: An impact printer (10) in which the action of a rotatable cam assembly (50) positions a plurality of type racks (22), enables printing and indexes paper (12) prior to restoring the type racks to the home position. Teeth (54) on the cam assembly engage teeth (30) on the type racks for positioning thereof and an extended tooth (62) on the cam assembly causes impact of the racks against a platen (14) which is caused to be rotated by movement of the cam assembly to index the paper to the next print line.

Abstract translation: 一种冲击式打印机（10），其中旋转凸轮组件（50）的作用定位多个类型的机架（22），使得能够在将类型的机架恢复到原始位置之前打印和索引纸张（12）。 凸轮组件上的齿（54）接合在类型齿条上的齿（30），用于定位它们，并且凸轮组件上的延伸齿（62）使机架抵靠压板（14）的冲击，压板（14）被移动 的凸轮组件将纸张索引到下一个打印行。

公开(公告)号：WO1981001637A1

公开(公告)日：1981-06-11

申请号：PCT/US1980001527

申请日：1980-11-13

Applicant: NCR CORP

Inventor： NCR CORP ,  CHARI V

IPC: H03K13/00

CPC classification number: H04L25/4904

Abstract: A data recovery circuit (20) for use in a data processing system where plural subsystems are linked by a bit serial transmission line. The data transmitted over the bit serial transmission line is in the form of a phase encoded (PE) pulse signal (ENDATA). The data recovery circuit (20) includes a time delay circuit for delaying the PE pulse signal (ENDATA) by a three-quarter bit period. The three-quarter bit period delay signal permits the generation of a control clock signal. The control clock signal is used in sampling the PE pulse signal at three-quarter bit period points in order to generate a control signal (CNTRL) that indicates the absence or presence of a transition at the midpoint of each bit period of the PE pulse signal (ENDATA). The control signal (CNTRL) is used to generate a recovered clock signal (RCLK) by logically combining the control signal (CNTRL) with the PE pulse signal (ENDATA) and a one-half bit period delayed PE pulse signal (HBTD). The control signal (CNTRL) is also used to generate a recovered data signal (RDATA) by clocking the control signal (CNTRL) into two cascaded flip-flops and logically combining the outputs of the two cascaded flip-flops.

公开(公告)号：WO1981001485A1

公开(公告)日：1981-05-28

申请号：PCT/US1980001523

申请日：1980-11-12

Applicant: NCR CORP

Inventor： NCR CORP ,  DALTON P ,  BERGSTEDT L

IPC: H01L27/02

CPC classification number: H01L21/28273 ,  H01L21/823456 ,  H01L21/823462 ,  H01L29/7838

Abstract: A pair of narrow channel IGFET devices (10A, 10B) having separate insulated gate electrode structures (19A, 19B) formed over narrow channel regions (28A, 28B) of a substrate (11) flanking a central enhancement region (27). Methods of forming the narrow channel regions using a single photolithography step and forming separate gate electrode structures overlying each using alternative processes, each generally involving two photolithography steps, are set forth.

Abstract translation: 一对窄通道IGFET器件（10A，10B）具有分开的绝缘栅电极结构（19A，19B），形成在中心增强区域（27）侧面的衬底（11）的窄通道区域（28A，28B）上。 使用单个光刻步骤形成窄通道区域的方法，并且使用各自通常涉及两个光刻步骤的替代工艺形成分别覆盖每个的栅电极结构。

公开(公告)号：WO1981000487A1

公开(公告)日：1981-02-19

申请号：PCT/US1980001020

申请日：1980-08-07

Applicant: NCR CORP

Inventor： NCR CORP ,  DHAM V ,  TRUDEL M

IPC: H01L21/324

CPC classification number: H01L27/11517 ,  H01L21/3003

Abstract: In a method for manufacturing a semiconductor non-volatile SNOS or SONOS memory device having a gate structure which includes a gate oxide layer (11) provided on a semiconductor substrate (16), a nitride layer (12) provided on the gate oxide layer (11) and a polysilicon gate electrode (14) overlying the nitride layer (12), the device is annealed in hydrogen, in an annealing vessel (40), typically for 15-60 minutes at 600-1100`C.

Abstract translation: 在具有栅极结构的半导体非易失性SNOS或SONOS存储器件的制造方法中，所述栅极结构包括设置在半导体衬底（16）上的栅极氧化物层（11），设置在所述栅极氧化物层上的氮化物层（12） 11）和覆盖氮化物层（12）的多晶硅栅电极（14），该装置在退火容器（40）中在氢气中退火，通常在600-1100℃下15-60分钟。

公开(公告)号：WO1981000161A1

公开(公告)日：1981-01-22

申请号：PCT/US1980000820

申请日：1980-06-27

Applicant: NCR CORP

Inventor： NCR CORP ,  DAVISON A ,  LEWIS W

IPC: G06F13/00

CPC classification number: G06F12/04 ,  G06F11/1056 ,  G06F13/16

Abstract: A memory system (10) having a word-addressable memory (12, 14) and bit changing circuitry (35) for changing or updating individual bits within the data words stored in the memory. The memory includes a primary memory (12) and a copy memory (14). The copy memory (14) stores duplicates of the data words stored in the primary memory (12). The bit changing circuitry (35) receives a word having a bit to be changed from the copy memory (14) and returns the word, including the changed bit, to both the primary memory (12) and copy memory (14). The memory system may constitute a parity memory system in a data processor.

公开(公告)号：WO1980002349A1

公开(公告)日：1980-10-30

申请号：PCT/US1980000364

申请日：1980-04-04

Applicant: NCR CORP

Inventor： NCR CORP ,  OOSTERBAAN D ,  WILLIAMS G

IPC: H04L09/02

CPC classification number: H04L9/0662 ,  H04L9/0637 ,  H04L2209/12 ,  H04L2209/34

Abstract: Enciphering/deciphering apparatus having two pseudo-random bit generators (16, 28) which are cross-coupled in the enciphering mode by logic circuitry (10, 14, 18, 20, 22, 26). An input data signal is directed to the input of each bit generator by a pair of summing devices (18, 20). The data signal is also logically combined with the output of each bit generator by a second pair of summing devices (30, 32). In the deciphering mode the pseudo-random bit generators are connected in a feedback configuration by logic circuitry (12, 14, 18, 20, 24, 26). The to-be-decoded signal is directed to the input of each bit generator by the first pair of summing devices (18, 20). The to-be-decoded signal is also logically combined with the output of each bit generator by the second pair of summing devices (30, 32) to provide the decoded signal.

Abstract translation: 具有通过逻辑电路（10,14,18,20,22,26）以加密模式交叉耦合的两个伪随机位发生器（16,28）的加密/解密装置。 输入数据信号通过一对求和装置（18,20）指向每个位发生器的输入。 数据信号还通过第二对求和装置（30,32）与每个位发生器的输出逻辑地组合。 在解密模式中，伪随机位发生器通过逻辑电路（12,14,18,20,24,26）以反馈配置连接。 被解码的信号被第一对求和装置（18,20）引导到每个位发生器的输入端。 待解码信号还通过第二对求和装置（30,32）与每个位发生器的输出逻辑地组合以提供解码信号。

公开(公告)号：WO1980002335A1

公开(公告)日：1980-10-30

申请号：PCT/US1980000337

申请日：1980-03-27

Applicant: NCR CORP

Inventor： NCR CORP ,  HERBORN P

IPC: G03D07/00

CPC classification number: G03D7/00

Abstract: A diazo film developing apparatus and method in which an exposed diazo film (36) is moved through a heated developing chamber (16) and is contacted by ammonia vapor which develops the film. Aqueous ammonia is fed into a separation chamber (20) connected with said developing chamber (16) and the ammonia is separated from the water by heating and introduced into the developing chamber (16). A thermal control means (62) is provided between said developing chamber (16) and said separation chamber (20) to maintain a temperature differential therebetween, said separation chamber (20) having a temperature lower than the temperature of the developing chamber (16). In the preferred embodiment the separation chamber is in the form of a cavity or trough in the bottom of the developing chamber (16).

Abstract translation: 一种重氮膜显影装置和方法，其中暴露的重氮膜（36）移动通过加热的显影室（16）并与形成膜的氨蒸气接触。 氨水被供给到与所述显影室（16）连接的分离室（20）中，氨通过加热与水分离并被引入显影室（16）。 在所述显影室（16）和所述分离室（20）之间设置有热控制装置（62）以保持它们之间的温差，所述分离室（20）的温度低于显影室（16）的温度， 。 在优选实施例中，分离室在显影室（16）的底部中是空腔或凹槽的形式。

公开(公告)号：WO1980002080A1

公开(公告)日：1980-10-02

申请号：PCT/US1980000265

申请日：1980-03-13

Applicant: NCR CORP

Inventor： NCR CORP ,  ADVANI J ,  WHITELY R ,  HALE W ,  PAGANINI B

IPC: G06K09/46

CPC classification number: G07C9/0015 ,  G06K9/00167 ,  G06K9/522

Abstract: A method and apparatus for verifying the identity of a person by first establishing and storing in a storage unit (116) a reference vector based upon predetermined characteristics derived from a number of handwritten signature samples. In the verification mode, a person whose identity is to be verified enters an identification number on a keyboard (144) thereby selecting his reference vector from the storage unit (116). The person then writes his signature on a signature pad (108), the written signature generating an analog waveform which is digitized, the digitized representation then being compressed. Thereafter, parameters dependent on Haar coefficients and on physical features are computed to provide a vector which is compared with the reference vector utilizing a comparison threshold which has been predetermined for that person.

公开(公告)号：WO1980001424A1

公开(公告)日：1980-07-10

申请号：PCT/US1979001126

申请日：1979-12-27

Applicant: NCR CORP

Inventor： NCR CORP ,  PATEL N

IPC: G06F13/00

CPC classification number: G06F12/0864

Abstract: A memory system comprises a pair of RAM buffer memories (22, 24) coupled to a CCD main memory (20) to provide high-speed memory access to the memory by a processing means. Each buffer memory has stored therein a page of data transferred from the CCD main memory. Comparison means (76, 78) included in the system compares the page address in a memory request with the page address, located in address registers, of the data stored in the buffer memories. If a comparison is found, the designated buffer memory is accessed for a read/write operation at the addressed memory location. If no comparison is found, circuits (72, 92, 134) using the requested page address transfer the page in which the requested address is located from the CCD main memory to a RAM buffer memory for access by the processing means; the buffer memory to which the page is transferred is the buffer memory that was not accessed in the immediately preceding memory request. If a write operation had occured on a page stored in the buffer memories, the altered page is transferred back to the CCD main memory before a new page of data is transferred to the buffer memory.

Abstract translation: 存储器系统包括耦合到CCD主存储器（20）的一对RAM缓冲存储器（22,24），以通过处理装置向存储器提供高速存储器访问。 每个缓冲存储器中存储有从CCD主存储器传送的数据页。 包括在系统中的比较装置（76,78）将存储器请求中的页面地址与存储在缓冲存储器中的数据的地址寄存器中的页面地址进行比较。 如果发现比较，则在指定的存储器位置访问指定的缓冲存储器用于读/写操作。 如果没有发现比较，使用请求的页地址的电路（72,92,134）将请求的地址所在的页面从CCD主存储器传送到RAM缓冲存储器，以供处理装置访问; 页面传输到的缓冲存储器是在前一个存储器请求中未被访问的缓冲存储器。 如果在存储在缓冲存储器中的页面上发生了写入操作，则在新的数据页被传送到缓冲存储器之前，改变的页面被传送回到CCD主存储器。

公开(公告)号：WO1980001328A1

公开(公告)日：1980-06-26

申请号：PCT/US1979001124

申请日：1979-12-18

Applicant: NCR CORP

Inventor： NCR CORP ,  HUI P

IPC: G11C13/04

CPC classification number: G11B7/0953 ,  G11B7/00736 ,  G11B27/034 ,  G11B27/22 ,  G11B27/3027 ,  G11B27/329 ,  G11B2220/218

Abstract: A method of recording data on an optical disc (10) having already recorded thereon one or more bands or segments of data each comprising a plurality of tracks and having a portion for producing an end-of-band signal indicative of the last recorded track the respective band. After sensing the end-of-band signal of the last recorded band, a relative radial movement is brought about between a recording means and the disc (10) by a distance corresponding to a predetermined number of tracks to produce a gap (18) between the last recorded band and the next band to be recorded and recording of the next band is then commenced. The distance is determined experimentally with a view to compensating for the eccentricity errors likely to be encountered in practice when recording on an optical disc (10) at a predetermined density.