Abstract:
A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.
Abstract:
A conductive bump assembly may include a passive substrate. The conductive bump assembly may also include a conductive bump pad supported by the passive substrate and surrounded by a first passivation layer opening. The conductive bump assembly may further include a second passivation layer opening on the passive substrate. The second passivation layer opening may be merged with the first passivation layer opening surrounding the conductive bump pad proximate an edge of the passive substrate. The conductive bump assembly may also include a conductive bump on the conductive bump pad.
Abstract:
A device includes an acoustic resonator (220) embedded within an encapsulating structure (202) that at least partially encapsulates the acoustic resonator (204). The device includes an inductor (211, 229, 231, 233, 235, 212, 213, 214, and 215) electrically connected to the acoustic resonator. At least a portion of the inductor (211, 229, 231, 233, and 235) is embedded in the encapsulating structure. The capacitor may comprise a metal-insulator-metal, MIM, capacitor including a first metal layer (215) and a second metal layer (253). The inductor may include an interconnect (211, 229, 231, 233) disposed proximate to the encapsulating structure, and the first metal layer of the MIM capacitor may include the interconnect. The acoustic resonator may include a resonator structure (208) and a capping layer (228) between the resonator structure (208) and the encapsulating structure, the capping layer defining a cavity (227) in which the resonator structure is configured to vibrate. The encapsulating structure may be formed by using a glass molding process to enclose the acoustic resonator in a glass substrate.
Abstract:
An integrated circuit (IC) includes a first semiconductor device on a glass substrate. The first semiconductor device includes a first semiconductive region of a bulk silicon wafer. The IC includes a second semiconductor device on the glass substrate. The second semiconductor device includes a second semiconductive region of the bulk silicon wafer. The IC includes a through substrate trench between the first semiconductive region and the second semiconductive region. The through substrate trench includes a portion disposed beyond a surface of the bulk silicon wafer.
Abstract:
A three-dimensional (3D) orthogonal inductor pair (700) is embedded in and supported by a substrate (701), and has a first inductor (702) having a first coil that winds around a first winding axis and a second inductor (706) having a second coil that winds around a second winding axis. The second winding axis is orthogonal to the first winding axis. The second winding axis intersects the first winding axis at an intersection point that is within the substrate.
Abstract:
Some novel features pertain to an integrated device package (e.g., die package) that includes a package substrate, a die, an encapsulation layer and a first set of metal layers. The package substrate includes a first surface and a second surface. The die is coupled to the first surface of the package substrate. The encapsulation layer encapsulates the die. The first set of metal layers is coupled to a first exterior surface of the encapsulation layer. In some implementations, the first set of metal layers is configured to operate as a die-to-wire connector of the integrated device package. In some implementations, the integrated device package includes a second set of metal layers coupled to the second surface of the package substrate. In some implementations, the integrated device package includes a second set of metal layers coupled to a second exterior surface of the encapsulation layer.
Abstract:
An apparatus is disclosed that includes a frequency multiplexer circuit coupled to an input node and configured to receive an input signal via the input node. The frequency multiplexer circuit comprises a first filter circuit, a second filter circuit, and a third filter circuit. The apparatus also includes a switching circuit that is configurable to couple at least two of a first output of the first filter circuit, a second output of the second filter circuit, or a third output of the third filter circuit to a single output port.
Abstract:
FACE-UP SUBSTRATE INTEGRATION WITH SOLDER BALL CONNECTION IN SEMICONDUCTOR PACKAGE Systems and methods relate to a semiconductor package 200 comprising a first substrate or a 2D passive-on-glass (POG) structure with a passive component 204 and a first set of one or more package pads 203 formed on a face of a glass substrate 202. The semiconductor package also includes a second or laminate substrate 207 with a second set of one or more package pads 205 formed on a face of the second or laminate substrate. Solder balls 206 are dropped, configured to contact the first set of one or more package pads with the second set of one or more package pads, wherein the first substrate or the 2D POG structure is placed face-up on the face of the second or laminate substrate. A printed circuit board (PCB) 208 can be coupled to a bottom side of the second or laminate substrate.
Abstract:
A 3D nested transformer includes a substrate having a set of through substrate vias daisy chained together with a set of traces. At least some of the through substrate vias have first and second conductive regions. The set of traces also includes a first set of traces coupling together at least some of the first conductive regions of the through substrate vias, and a second set of traces coupling together at least some of the second conductive regions of the through substrate vias.
Abstract:
Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to be occupied by a interconnect material (e.g., solder ball). The substrate also includes a first metal layer coupled to a first side wall of the first cavity. The substrate further includes a first integrated passive device (IPD) on a first surface of the substrate, the first IPD coupled to the first metal layer. In some implementations, the substrate is a glass substrate. In some implementations, the first IPD is one of at least a capacitor, an inductor and/or a resistor. In some implementations, the semiconductor device further includes a second integrated passive device (IPD) on a second surface of the substrate. The second IPD is coupled to the first metal layer.