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    33.
    发明专利
    未知

    公开(公告)号：DE69220632D1

    公开(公告)日：1997-08-07

    申请号：DE69220632

    申请日：1992-08-27

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G06F1/24 ,  H03K17/00 ,  H03K17/22

    Abstract: A power-on reset circuit utilizes capacitive couplings and does not establish any static current path bewteen the supply rails. The circuit has a null static consumption and may be advantageously integrated in CMOS micrologics. Moreover the circuit is insensitive to rebounds on the supply rails and to internal and external noise.

    34.
    发明专利
    未知

    公开(公告)号：DE69115952T2

    公开(公告)日：1996-09-19

    申请号：DE69115952

    申请日：1991-02-07

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G11C11/419 ,  G11C16/06 ,  G11C16/28 ,  G11C17/00 ,  G11C17/18

    Abstract: A sense circuit for reading EPROM and ROM type memory cells employs a circuit for generating an offsetting current which is exempt of error during transients and which thus permits to achieve a reduced access time. On the other hand, the sense circuit maintains the intrinsic advantages of a current-offset sensing architecture which is represented by a substantially unlimited operating voltage range toward the maximum value VCCmax. The current generating circuit is driven by means of a supplementary row of cells which is decoded at every reading and which replicates, during transients, the behaviour of the row selected for the reading.

    35.
    发明专利
    未知

    公开(公告)号：IT1246241B

    公开(公告)日：1994-11-17

    申请号：IT8360790

    申请日：1990-02-23

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G11C16/06 ,  G11C11/419 ,  G11C16/28 ,  G11C17/00 ,  G11C17/18 ,  G11C

    Abstract: A sense circuit for reading EPROM and ROM type memory cells employs a circuit for generating an offsetting current which is exempt of error during transients and which thus permits to achieve a reduced access time. On the other hand, the sense circuit maintains the intrinsic advantages of a current-offset sensing architecture which is represented by a substantially unlimited operating voltage range toward the maximum value VCCmax. The current generating circuit is driven by means of a supplementary row of cells which is decoded at every reading and which replicates, during transients, the behaviour of the row selected for the reading.

    37.
    发明专利
    未知

    公开(公告)号：IT8883645D0

    公开(公告)日：1988-06-28

    申请号：IT8364588

    申请日：1988-06-28

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： OLIVO MARCO ,  PASCUCCI LUIGI ,  VILLA CORRADO

    IPC: G11C5/14 ,  G11C16/30 ,  H02M3/07

    Abstract: A wholly integrated, multistage, CMOS voltage multiplier utilizes as a diode structure for transferring electric charge from an input node to an output node of each stage an enhancement type MOS transistor, the gate of which is coupled to the same switching phase to which the output capacitor of the stage is connected by means of a coupling capacitor. During a semicycle of charge transfer through said MOS transistor, the coupling capacitor charges through a second MOS transistor of the same type and having the same threshold of said charge transfer MOS transistor, connected in a diode configuration between the output node of the stage and the gate of the charge transfer MOS transistor, in order to cut-off the latter when reaching a voltage lower than the voltage reached by the output node by a value equal to the threshold value of said second transistor. In this way, a significant voltage drop across the charge transfer transistor is efficiently eliminated, thus allowing the generation of a sufficiently high output voltage though having available a relatively low supply voltage.

    38.
    发明专利
    未知

    公开(公告)号：DE69412230T2

    公开(公告)日：1999-04-08

    申请号：DE69412230

    申请日：1994-02-17

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

    Abstract: A method for programming redundancy registers in a column redundancy integrated circuitry for a semiconductor memory device with columns of memory elements grouped together to form portions of a bidimensional array of memory elements, the column redundancy circuitry comprising at least one plurality of non-volatile memory registers (RR1-RR4) each one associated to a respective redundancy column of redundancy memory elements and each one programmable to store an address of a defective column and an identifying code (MCS7-MCS10) for identifying the portion of the bidimensional array to which the defective column belongs, provides for supplying each non-volatile memory register (RR1-RR4) with column address signals (CABUS) and with a first subset (R1-R4) of row address signals (RABUS), which when one of the non-volatile memory registers (RR1-RR4) is to be programmed carry the address of a defective column and said identifying code (MCS7-MCS10) respectively, and for activating one signal of a second subset (R5-R8) of the row address signals (RABUS), supplied to programming selection means (6), for selecting one respective non-volatile memory register (RR1-RR4) of said plurality to cause the data carried by the column address signals (CABUS) and by the first subset (R1-R4) of the row address signals to be programmed into said one respective non-volatile memory register (RR1-RR4).

    39.
    发明专利
    未知

    公开(公告)号：DE69318842D1

    公开(公告)日：1998-07-02

    申请号：DE69318842

    申请日：1993-12-02

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  GOLLA CARLA MARIA ,  MACCARRONE MARCO

    IPC: G11C8/10 ,  G11C16/06 ,  G11C17/00 ,  G11C8/00

    Abstract: A memory line decoding driver (1) is so biased that the P channel pull-up transistor (6) biasing the final inverter (5) conducts a high current during the line address transient phase, for rapidly charging the input of the final inverter, and is turned on weakly during the static phase between one address phase and another, for reducing current consumption. For which purpose, a voltage modulating stage (18) alternatively connects the gate terminal of the pull-up transistor (6) to a capacitor (37), with which the charge is distributed, and to the supply (VPC).

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