公开(公告)号：DE69428894T2

公开(公告)日：2002-04-25

申请号：DE69428894

申请日：1994-08-02

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L29/78 ,  H01L29/739

Abstract: A power device integrated structure comprises a semiconductor substrate (5) of a first conductivity type, a semiconductor layer (3,4) of a second conductivity type superimposed over said substrate (5), a plurality of first doped regions (2) of the first conductivity type formed in the semiconductor layer (3,4), and a respective plurality of second doped regions (11) of the second conductivity type formed inside the first doped regions (2); the power device comprises: a power MOSFET (M) having a first electrode region represented by the second doped regions (11) and a second electrode region represented by the semiconductor layer (3,4); a first bipolar junction transistor (T2) having an emitter, a base and a collector respectively represented by the substrate (5), the semiconductor layer (3,4) and the first doped regions (2); and a second bipolar junction transistor (T1) having an emitter, a base and a collector respectively represented by the second doped regions (11), the first doped regions (2) and the semiconductor layer (3,4); the doping profiles of the semiconductor substrate (5), the semiconductor layer (3,4), the first doped regions (2) and the second doped regions (11) are such that the first and second bipolar junction transistors (T2,T1) have respective first and second common base current gains sufficiently high to cause said bipolar junction transistors to be biased in the high injection region, so that carriers are injected from the substrate (5) into the semiconductor layer (3,4) and from the second doped regions (11), through the first doped regions (2), into the semiconductor layer (3,4), the conductivity of the semiconductor layer (3,4) is thus modulated not only by the injection of minority carriers from the substrate (5), but also by majority carriers injected from the doped regions (11) into the first doped regions (2) and collected by the semiconductor layer (3,4). The first and second common base current gains summed are less than unity to prevent a parasitic thyristor from triggering on. The power device functions as an IGBT, having a reduced on-state voltage.

公开(公告)号：DE69523576D1

公开(公告)日：2001-12-06

申请号：DE69523576

申请日：1995-06-16

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： SANTANGELO ANTONELLO ,  FERLA GIUSEPPE

IPC: H01L21/331 ,  H01L29/49 ,  H01L29/739 ,  H01L29/78 ,  H01L23/00 ,  H01L29/43

Abstract: An electronic semiconductor device (20) with a control electrode (19) consisting of self-aligned polycrystalline silicon (4) and silicide (12), of the type in which said control electrode (19) is formed above a portion (1) of semiconductor material which accommodates active areas (9) of the device (20) laterally with respect to the electrode, has the active areas (9) at least partially protected by an oxide layer (10) while the silicide layer (12) is obtained by means of direct reaction between a metal film deposited on the polycrystalline silicon (4) and on the oxide layer (10).

公开(公告)号：DE69229927T2

公开(公告)日：2000-01-20

申请号：DE69229927

申请日：1992-03-17

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO FRISINA FERR ,  FERLA GIUSEPPE

IPC: H01L21/22 ,  H01L21/322 ,  H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/07 ,  H01L27/082 ,  H01L29/732 ,  H01L29/861

Abstract: The structure consists of a single chip (1) of semiconductor material, which comprises an area (32) having a high lifetime of the minority carriers, which constitutes a bipolar power device with high current density, and at least one area (20, 21; 20', 21') with a reduced lifetime of the minority carriers, which constitutes a fast diode.

公开(公告)号：DE69109468T2

公开(公告)日：1995-12-14

申请号：DE69109468

申请日：1991-05-23

Applicant: SGS THOMSON MICROELECTRONICS ,  ANSALDO TRASPORTI SPA

Inventor： FERLA GIUSEPPE ,  RONSISVALLE CESARE ,  ZANI PIER ENRICO

IPC: H01L25/07 ,  H01L23/051 ,  H01L23/50 ,  H01L23/525 ,  H01L25/18 ,  H01L23/522

公开(公告)号：IT8922891D0

公开(公告)日：1989-12-29

申请号：IT2289189

申请日：1989-12-29

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FERLA GIUSEPPE ,  MAGRO CARMELO ,  LANZA PAOLO

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L

Abstract: Process for the manufacture of power-MOS semiconductor devices which achieve high cell density by the use of self-aligning techniques and photographic exposure equipment of the stepper type. The process calls for definition and formation of the source by a complementary spacer technique and metallization of the source and gate contact areas by silicides after formation of spacers on the gate wall (FIG. 11).

公开(公告)号：IT8921281D0

公开(公告)日：1989-07-24

申请号：IT2128189

申请日：1989-07-24

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FERLA GIUSEPPE ,  LANZA PAOLO ,  MAGRO CARMELO

IPC: H01L29/78 ,  H01L21/033 ,  H01L21/265 ,  H01L21/32 ,  H01L21/336

Abstract: Along the outline of a first doped region of a first mask is formed using the spacer technology, said mask being made up of a dielectric opposing to the oxygen diffusion. Another mask is created within this first mask, using a process of selective thermal oxidation. The second mask is used to implant dopant into a second region which will only be defined along the outlines of the first region.

公开(公告)号：DE3855603T2

公开(公告)日：1997-03-13

申请号：DE3855603

申请日：1988-12-16

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FRISINA FERRUCCIO ,  FERLA GIUSEPPE

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H01L29/739 ,  H01L29/78 ,  H01L29/72 ,  H01L21/82

Abstract: A description is given of two versions of an integrated structure in the emitter switching configuration comprising a high-voltage bipolar power transistor and a low-voltage MOS power transistor. In the vertical MOS version, the emitter region of the bipolar transistor is completely buried, partly in a first N- epitaxial layer and partly in a second N epitaxial layer; the MOS is located above the emitter region. The bipolar is thus a completely buried active structure. In the horizontal MOS version, in a N- epitaxial layer there are two P+ regions, the first, which constitutes the base of the bipolar transistor, receives the N+ emitter region of the same transistor; the second receives two N+ regions which constitute the MOS source and drain regions, respectively; the front of the chip is provided with metal plating to ensure the connection between the MOS drain and the bipolar emitter contacts.

公开(公告)号：DE69007449T2

公开(公告)日：1994-08-25

申请号：DE69007449

申请日：1990-12-24

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FERLA GIUSEPPE ,  MAGRO CARMELO ,  LANZA PAOLO

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L29/784

Abstract: Process for the manufacture of power-MOS semiconductor devices which achieve high cell density by the use of self-aligning techniques and photographic exposure equipment of the stepper type. The process calls for definition and formation of the source by a complementary spacer technique and metallization of the source and gate contact areas by silicides after formation of spacers on the gate wall (FIG. 11).

公开(公告)号：DE69007449D1

公开(公告)日：1994-04-21

申请号：DE69007449

申请日：1990-12-24

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FERLA GIUSEPPE ,  MAGRO CARMELO ,  LANZA PAOLO

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L29/784

Abstract: Process for the manufacture of power-MOS semiconductor devices which achieve high cell density by the use of self-aligning techniques and photographic exposure equipment of the stepper type. The process calls for definition and formation of the source by a complementary spacer technique and metallization of the source and gate contact areas by silicides after formation of spacers on the gate wall (FIG. 11).

公开(公告)号：IT1231300B

公开(公告)日：1991-11-28

申请号：IT2128189

申请日：1989-07-24

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FERLA GIUSEPPE ,  LANZA PAOLO ,  MAGRO CARMELO

IPC: H01L29/78 ,  H01L21/033 ,  H01L21/265 ,  H01L21/32 ,  H01L21/336 ,  H01L

Abstract: Along the outline of a first doped region of a first mask is formed using the spacer technology, said mask being made up of a dielectric opposing to the oxygen diffusion. Another mask is created within this first mask, using a process of selective thermal oxidation. The second mask is used to implant dopant into a second region which will only be defined along the outlines of the first region.