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    MEMOIRE NON VOLATILE A ECRITURE RAPIDE
    31.
    发明专利
    MEMOIRE NON VOLATILE A ECRITURE RAPIDE 未知

    公开(公告)号：FR2915829A1

    公开(公告)日：2008-11-07

    申请号：FR0703153

    申请日：2007-05-02

    Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS SRL

    Inventor： LA ROSA FRANCESCO ,  CONTE ANTONINO

    IPC: G11C16/10 ,  G06K19/07

    Abstract: L'invention concerne un procédé d'écriture de données dans une mémoire non volatile (MA, XA) comportant des cellules mémoire devant être effacées avant d'être écrites. Le procédé comprend les étapes consistant à prévoir une zone mémoire principale non volatile (MA) comprenant des pages cibles, prévoir une zone mémoire auxiliaire non volatile (XA) comprenant des pages auxiliaires, prévoir une table de correspondance (VAM) pour associer à une adresse (RAD) de page cible invalide une adresse (XAD) de page auxiliaire valide, et, en réponse à une commande (CMD) d'écriture d'une donnée dans une page cible écrire la donnée ainsi que l'adresse de la page cible dans une première page auxiliaire effacée, invalider la page cible, et mettre à jour la table de correspondance.

    MEMOIRE NON VOLATILE A SECTEURS AUXILIAIRES TOURNANTS
    32.
    发明专利
    MEMOIRE NON VOLATILE A SECTEURS AUXILIAIRES TOURNANTS 未知

    公开(公告)号：FR2915828A1

    公开(公告)日：2008-11-07

    申请号：FR0703152

    申请日：2007-05-02

    Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS SRL

    Inventor： LA ROSA FRANCESCO ,  CONTE ANTONINO

    IPC: G11C16/10 ,  G06K19/07

    Abstract: L'invention concerne un procédé d'écriture de données dans une mémoire non volatile. Le procédé comprend les étapes consistant à prévoir, dans la mémoire, une zone mémoire principale (MA) non volatile comprenant des pages cible, une zone mémoire auxiliaire (XA) non volatile comprenant des pages auxiliaires, et, dans la zone mémoire auxiliaire : un secteur courant (CUR) comprenant des pages auxiliaires effacées utilisables pour écrire des données, un secteur de sauvegarde (ERM) comprenant des pages auxiliaires contenant des données rattachées à des pages cible à effacer ou en cours d'effacement, un secteur de transfert (CTM) comprenant des pages auxiliaires contenant des données à transférer dans des pages cible effacées, et un secteur indisponible (UNA) comprenant des pages auxiliaires à effacer ou en cours d'effacement. Application notamment aux mémoires Flash.

    34.
    发明专利
    未知

    公开(公告)号：IT1319395B1

    公开(公告)日：2003-10-10

    申请号：ITMI992149

    申请日：1999-10-14

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONTE ANTONINO ,  GAIBOTTI MAURIZIO ,  ZERILLI TOMMASO

    IPC: G11C7/06 ,  G11C7/14

    Abstract: A bias circuit for read amplifier circuits for memories includes at least one first circuit branch formed by a first pair of MOS transistors connected between a supply voltage and ground. The first pair of MOS transistors includes a P-channel diode connected transistor and an N-channel transistor connected in series, with an enable transistor interposed therebetween. The first circuit branch drives a capacitive load for coupling to the supply voltage. The bias circuit further includes reference current amplifier circuit branches for amplifying a reference current which flows in the first circuit branch for charging the capacitive load. A circuit portion, which controls the charging current of the capacitive load, includes a feedback loop between the reference current amplifier circuit branches and the capacitive load.

    38.
    发明专利
    未知

    公开(公告)号：DE602004003465D1

    公开(公告)日：2007-01-11

    申请号：DE602004003465

    申请日：2004-02-19

    Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS SRL

    Inventor： DEMANGE NICOLAS ,  CONTE ANTONINO ,  PRECISO SALVATORE ,  SIGNORELLO ALFREDO

    IPC: G11C7/14 ,  G01N27/00 ,  G11C7/06 ,  G11C7/10 ,  G11C16/28

    Abstract: A sensing circuit (120) for sensing currents, including at least one sense amplifier (122), comprising: a measure circuit branch (132i), having a measure node for receiving an input current (Ic) to be sensed, for converting the input current into a corresponding input voltage (V-); at least one comparison circuit branch (132o), having a comparison node for receiving a comparison current (Igs), for converting the comparison current into a corresponding comparison voltage (V+); and at least one voltage comparator (140) for comparing the input and comparison voltages, and means (N3s,135; N3s,135';N3s,135" ) for generating the comparison current based on a reference current (Ir), said means comprising: at least one voltage generator (135;135';135'') for receiving the reference current and for generating a corresponding sense amplifier biasing voltage (Vsab); and means (N3s) for converting the sense amplifier biasing voltage into the comparison current. The at least one voltage generator includes a first circuit branch (232i), having a first node for receiving the reference current, for converting the reference current into a corresponding reference voltage (Vref), a second circuit branch (232o), having a second node for receiving a regulation current (Ii), in current mirror configuration with the first circuit branch for mirroring a current (Img) corresponding to the reference current, the second circuit branch generating by conversion a non-regulated voltage (Vgen) corresponding to the mirrored current and to the regulation current, and voltage regulator means (N3g,240) receiving the reference voltage and the non-regulated voltage for regulating the sense amplifier biasing voltage by controlling the non-regulated voltage through the regulation current.

    39.
    发明专利
    未知

    公开(公告)号：DE60123925D1

    公开(公告)日：2006-11-30

    申请号：DE60123925

    申请日：2001-04-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONTE ANTONINO ,  CONCEPITO ORESTE

    IPC: G05F3/22 ,  G05F3/24

    Abstract: The present invention relates to a current reference circuit for low supply voltages comprising a current source (I), connected at a side to a supply voltage (Vcc) and to the other side to a series (21) composed by a resistance (R2) and diode (D1), said diode (D1) having the cathode electrode connected to the ground and the anode electrode connected with said resistance (R2), characterized in that to comprise also a transistor (M1) and an operational amplifier (OP), said transistor (M1) having the gate electrode connected to the output of said operational amplifier (OP), said transistor (M1) having the source electrode connected to the ground, said transistor (M1) having the drain electrode connected to the positive electrode of said operational amplifier (OP), with said current source (I) and with said series (21), said operational amplifier (OP) having the negative electrode connected to a band gap reference voltage (VBG).

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