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公开(公告)号：DE602004003465D1
公开(公告)日：2007-01-11
申请号：DE602004003465
申请日：2004-02-19
Applicant: ST MICROELECTRONICS SA , ST MICROELECTRONICS SRL
Inventor： DEMANGE NICOLAS , CONTE ANTONINO , PRECISO SALVATORE , SIGNORELLO ALFREDO
Abstract: A sensing circuit (120) for sensing currents, including at least one sense amplifier (122), comprising: a measure circuit branch (132i), having a measure node for receiving an input current (Ic) to be sensed, for converting the input current into a corresponding input voltage (V-); at least one comparison circuit branch (132o), having a comparison node for receiving a comparison current (Igs), for converting the comparison current into a corresponding comparison voltage (V+); and at least one voltage comparator (140) for comparing the input and comparison voltages, and means (N3s,135; N3s,135';N3s,135" ) for generating the comparison current based on a reference current (Ir), said means comprising: at least one voltage generator (135;135';135'') for receiving the reference current and for generating a corresponding sense amplifier biasing voltage (Vsab); and means (N3s) for converting the sense amplifier biasing voltage into the comparison current. The at least one voltage generator includes a first circuit branch (232i), having a first node for receiving the reference current, for converting the reference current into a corresponding reference voltage (Vref), a second circuit branch (232o), having a second node for receiving a regulation current (Ii), in current mirror configuration with the first circuit branch for mirroring a current (Img) corresponding to the reference current, the second circuit branch generating by conversion a non-regulated voltage (Vgen) corresponding to the mirrored current and to the regulation current, and voltage regulator means (N3g,240) receiving the reference voltage and the non-regulated voltage for regulating the sense amplifier biasing voltage by controlling the non-regulated voltage through the regulation current.
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公开(公告)号：DE69827109D1
公开(公告)日：2004-11-25
申请号：DE69827109
申请日：1998-02-13
Applicant: ST MICROELECTRONICS SRL
Inventor： GAIBOTTI MAURIZIO , DEMANGE NICOLAS
Abstract: Sense amplifier circuit for non-volatile memories, of the type apt to draw a reference current from a reference bitline and a cell current from a cell array bitline, and compare them by means of current-voltage converting means and an amplifying stage, said current-voltage converting means comprising also fixing means of a determined voltage on the reference bitline and on the cell array bitline, load circuit means for the reference bitline and the cell array bitline, current mirror circuits for mirroring the reference current into a input node of the amplifying stage and the cell current into a further input of said amplifying stage. According to the invention the load circuit means of the reference bitline (BLREF) and the mirroring means (MR) of the reference current are different circuits and the reference bitline load circuit means are represented by a transistor (P3) which mirrors a predetermined current (IP), generated outside of the sense amplifier circuit (3), in order to have a lower voltage drop on said load circuit means (P3).
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公开(公告)号：ITMI20020673A1
公开(公告)日：2003-09-29
申请号：ITMI20020673
申请日：2002-03-29
Applicant: ST MICROELECTRONICS SRL
Inventor： DEMANGE NICOLAS , TORRISI SALVATORE , SBERNO GIAMPIERO
IPC: G11C11/22
Abstract: A method and circuit for accessing a memory location comprising at least one respective ferroelectric storage unit of a matrix of ferroelectric storage units, the memory location is selected by connecting a first terminal of a ferroelectric storage element of the at least one respective storage unit to a respective access line to the memory location; at least another memory location to which is not intended to be accessed is also selected. A second terminal of the ferroelectric storage element is biased to a prescribed access electric potential, and an electric potential on the access line is sensed; the second terminal of the ferroelectric storage elements of the other memory location is also biased to the access potential.
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公开(公告)号：ITMI20011812D0
公开(公告)日：2001-08-24
申请号：ITMI20011812
申请日：2001-08-24
Applicant: ST MICROELECTRONICS SRL
Inventor： DEMANGE NICOLAS , TORRISI SALVATORE , SBERNO GIAMPIERO
IPC: G11C11/22
Abstract: A method of reading and restoring data stored in a ferroelectric memory cell is disclosed. The cell includes a first transistor and first ferroelectric capacitor connected, in series with each other, between a first bitline and an auxiliary line, a second transistor and second ferroelectric capacitor connected, in series with each other, between a second bitline and the auxiliary line, the first and second transistors having respective control terminals connected to a common wordline. The reading method includes precharging the first and second capacitors, applying a read pulse to the cell such that the state of the first capacitor is changed, reading the cell by a sensing means, and restoring the first capacitor to an initial state. Advantageously, the reading method further includes changing the state of the second capacitor during the step of restoring the first capacitor, and further restoring the second capacitor to an initial state, such that the voltages being applied to the transistors during any of the steps are lower than a voltage reference of the cell. Also disclosed is a method of writing and restoring data stored in a ferroelectric memory cell.
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公开(公告)号：ITMI20062211A1
公开(公告)日：2008-05-18
申请号：ITMI20062211
申请日：2006-11-17
Applicant: ST MICROELECTRONICS SRL
Inventor： CONTE ANTONINO , DEMANGE NICOLAS , DI MARTINO ALBERTO , LO GIUDICE GIANBATTISTA , MICCICHE MARIO
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Patent Agency Ranking
公开(公告)号：DE69834313D1
公开(公告)日：2006-06-01
申请号：DE69834313
申请日：1998-02-13
Applicant: ST MICROELECTRONICS SRL
Inventor： CONTE ANTONINO , DEMANGE NICOLAS
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公开(公告)号：ITMI20020793A1
公开(公告)日：2003-10-15
申请号：ITMI20020793
申请日：2002-04-15
Applicant: ST MICROELECTRONICS SRL
Inventor： DEMANGE NICOLAS , TORRISI SALVATORE , SBERNO GIAMPIERO
Abstract: A ferroelectric semiconductor memory includes an arrangement of memory units comprising at least one row of memory units. The memory units of the at least one row are associated with a respective word line of the arrangement. The arrangement of memory unit includes a plurality of local word lines branching off from the word line associated with the at least one row, each local word line being connected to a respective group of memory units of the line. Selective connection means allow to selectively connect one of the local word lines to the respective word line. The arrangement of memory units further includes a plurality of local plate biasing lines, each one associated with the memory units of a respective group of memory units, for selectively driving the memory units of the respective groups.
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公开(公告)号：ITMI20011812A1
公开(公告)日：2003-02-24
申请号：ITMI20011812
申请日：2001-08-24
Applicant: ST MICROELECTRONICS SRL
Inventor： DEMANGE NICOLAS , TORRISI SALVATORE , SBERNO GIAMPIERO
IPC: G11C11/22
Abstract: A method of reading and restoring data stored in a ferroelectric memory cell is disclosed. The cell includes a first transistor and first ferroelectric capacitor connected, in series with each other, between a first bitline and an auxiliary line, a second transistor and second ferroelectric capacitor connected, in series with each other, between a second bitline and the auxiliary line, the first and second transistors having respective control terminals connected to a common wordline. The reading method includes precharging the first and second capacitors, applying a read pulse to the cell such that the state of the first capacitor is changed, reading the cell by a sensing means, and restoring the first capacitor to an initial state. Advantageously, the reading method further includes changing the state of the second capacitor during the step of restoring the first capacitor, and further restoring the second capacitor to an initial state, such that the voltages being applied to the transistors during any of the steps are lower than a voltage reference of the cell. Also disclosed is a method of writing and restoring data stored in a ferroelectric memory cell.
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公开(公告)号：ITMI20020793D0
公开(公告)日：2002-04-15
申请号：ITMI20020793
申请日：2002-04-15
Applicant: ST MICROELECTRONICS SRL
Inventor： DEMANGE NICOLAS , TORRISI SALVATORE , SBERNO GIAMPIERO
Abstract: A ferroelectric semiconductor memory includes an arrangement of memory units comprising at least one row of memory units. The memory units of the at least one row are associated with a respective word line of the arrangement. The arrangement of memory unit includes a plurality of local word lines branching off from the word line associated with the at least one row, each local word line being connected to a respective group of memory units of the line. Selective connection means allow to selectively connect one of the local word lines to the respective word line. The arrangement of memory units further includes a plurality of local plate biasing lines, each one associated with the memory units of a respective group of memory units, for selectively driving the memory units of the respective groups.
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公开(公告)号：ITMI20020673D0
公开(公告)日：2002-03-29
申请号：ITMI20020673
申请日：2002-03-29
Applicant: ST MICROELECTRONICS SRL
Inventor： DEMANGE NICOLAS , TORRISI SALVATORE , SBERNO GIAMPIERO
IPC: G11C11/22
Abstract: A method and circuit for accessing a memory location comprising at least one respective ferroelectric storage unit of a matrix of ferroelectric storage units, the memory location is selected by connecting a first terminal of a ferroelectric storage element of the at least one respective storage unit to a respective access line to the memory location; at least another memory location to which is not intended to be accessed is also selected. A second terminal of the ferroelectric storage element is biased to a prescribed access electric potential, and an electric potential on the access line is sensed; the second terminal of the ferroelectric storage elements of the other memory location is also biased to the access potential.
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