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    31.
    发明专利
    未知

    公开(公告)号：DE60301119D1

    公开(公告)日：2005-09-01

    申请号：DE60301119

    申请日：2003-12-08

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  VINCENT EMMANUEL ,  BRUYERE SYLVIE ,  CANDELIER PHILIPPE ,  JACQUET FRANCOIS

    IPC: G11C14/00 ,  G11C17/14

    Abstract: The memory cell (10) comprises two inverter circuits (14,16) interconnected between the data nodes (N1,N2) so to form a memory circuit (12), two programming transistors (28,30) for implementing an irreversible degradation of the gate oxide layers of transistors (18,18'), and two transistors (32,34) for implementing the functioning of the memory cell after programming. Each inverter circuit (14,16) comprises supplementary MOS transistors (18,20;18',20') connected in series between a supply voltage source (VDD) and the ground circuit (22). Each inverter circuit comprises a p-MOS transistor (18,18') and an n-MOS transistor (20,20'), and the data nodes (N1,N2) are formed between the two transistors, n-MOS and p-MOS. The degraded MOS transistor is a transistor with thin gate oxide layer (GO1). The oxide layer is degraded at least locally so to obtain a variation of current through the transistor at the time of reading the cell. The programming transistors (28,30), or the diodes, are connected between the programming control line (PROG) and the transistors of the inverter circuits. The n-MOS programming transistors (28,30) ensure a selective connection of the gates of the transistors (18,18') to a programming voltage (VREF) at a level sufficient to cause the degradation of the gate oxide layers of the transistors. The inverter circuits are interconnected by the intermediary of a n-MOS transistor (32,34) connected to the control line (SRAM) of functioning the cell as the SRAM cell. The drain and the source electrodes of the transistors (32,34) are connected to the gates of the transistors of the inverter circuits.

    Memory element with a definite number of write cycles, comprises memory units of programmable read-only memory (PROM) type controlled by a chain of selection units
    32.
    发明专利
    Memory element with a definite number of write cycles, comprises memory units of programmable read-only memory (PROM) type controlled by a chain of selection units 未知

    公开(公告)号：FR2840443A1

    公开(公告)日：2003-12-05

    申请号：FR0206863

    申请日：2002-06-04

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  SCHOELLKOPF JEAN PIERRE ,  CANDELIER PHILIPPE

    IPC: G11C8/12 ,  G11C16/08 ,  G11C7/22

    Abstract: The memory element comprises a set of n memory units (10-1,....,10-n), each with an address bus, a data bus, and a control bus connected respectively to the main address bus, the main data bus and the main control bus. The memory units comprise the elements of fuse/antifuse type allowing an irreversible registering of information. The control chain comprises the selection units (12-1,....,12-n) each generating a selection signal, that is a Chip-Select (CSi), where i is from 1 to n, for one of the memory units (10i) in a manner to allow an exclusive access to the selected memory unit. The selection units switch automatically the selection of memory units following the detection of a predetermined condition. The memory element allows to implement an equivalent of a programmable memory of the type few times programmable (FTP), and in particular of type FLASH. A memory circuit (claimed) comprises the memory units of programmable type. The memory element comprises the programmable memory units (10-1,...,10-n) each receiving a Status Bit (SBi) which allows to store an information on the end of selection, and the predetermined condition corresponds to writing the Status Bit in the respective memory unit. The selection units are connected in a chain which allows to compute the selection signal for the memory unit of rank i, and two selection signals, direct and inverse, S(i) and SN(i), are transmitted and received by the selection unit of rank i+1. The selection unit is in two embodiments. In the first embodiment, teh selection unit comprises a bistable of type D, an inverter, and three AND gates. In the second embodiment, the selection unit comprises an inverter and a NOR gate. Each memory unit is implemented by a technology of type CMOS, and the fusible elements are constituted by capacitors with thin oxide layers.

    PROCEDE DE FABRICATION D'UN POINT MEMOIRE ANTI-FUSIBLE
    34.
    发明专利
    PROCEDE DE FABRICATION D'UN POINT MEMOIRE ANTI-FUSIBLE 未知

    公开(公告)号：FR2957457A1

    公开(公告)日：2011-09-16

    申请号：FR1051760

    申请日：2010-03-11

    Applicant: ST MICROELECTRONICS SA

    Inventor： CANDELIER PHILIPPE ,  LE ROUX ELISE

    IPC: H01L21/02 ,  H01L21/335 ,  H01L21/8239 ,  H01L27/108 ,  H01L29/78

    Abstract: L'invention concerne un procédé de fabrication d'un point mémoire (40) comprenant un transistor de sélection (11) et un transistor anti-fusible (13), dans une filière technologique adaptée à la fabrication de premier et second types de transistors MOS d'épaisseurs de grille distinctes, ce procédé comprenant les étapes suivantes : former le transistor de sélection (11) selon les étapes de fabrication de transistor à canal N du second type ; et former le transistor anti-fusible (13) essentiellement selon les étapes de fabrication de transistor à canal N du premier type, en modifiant l'étape suivante : au lieu de faire une implantation de type P dans la région de canal en même temps que dans les transistors à canal N du premier type, faire une implantation de type N dans la région de canal (27PGO1) en même temps que dans les transistors à canal P du premier type.

    CELLULE DE MEMOIRE VOLATILE PREENREGISTREE
    38.
    发明专利
    CELLULE DE MEMOIRE VOLATILE PREENREGISTREE 未知

    公开(公告)号：FR2877143A1

    公开(公告)日：2006-04-28

    申请号：FR0411360

    申请日：2004-10-25

    Applicant: ST MICROELECTRONICS SA

    Inventor： CANDELIER PHILIPPE ,  LASSEUGUETTE JEAN ,  FOURNEL RICHARD

    IPC: H01L27/11 ,  G11C14/00

    Abstract: L'invention a pour objet de proposer une cellule de mémoire de type SRAM capable de mémoriser de manière non volatile une donnée. Une cellule de mémoire comporte deux inverseurs 20 et 21 montés tête-bêche pour mémoriser un bit. Chaque inverseur 20 ou 21 comporte un transistor 24 ou 26 d'un premier type et un transistor 25 ou 27 d'un second type. La concentration de porteurs dans le canal de conduction du transistor 24 du premier type de l'un des inverseurs 20 est différente de la concentration de porteurs dans le canal de conduction du transistor 26 du premier type de l'autre des inverseurs 21 de sorte que les inverseurs aient des tensions de seuil différentes.

    Memory cell of type permanent static random-access memory (SRAM), comprises two interconnected inverter circuits and transistors for programming by degradation of gate oxide layers
    39.
    发明专利
    Memory cell of type permanent static random-access memory (SRAM), comprises two interconnected inverter circuits and transistors for programming by degradation of gate oxide layers 未知

    公开(公告)号：FR2849260A1

    公开(公告)日：2004-06-25

    申请号：FR0216558

    申请日：2002-12-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  VINCENT EMMANUEL ,  BRUYERE SYLVIE ,  CANDELIER PHILIPPE ,  JACQUET FRANCOIS

    IPC: G11C14/00 ,  G11C17/14 ,  G11C11/412 ,  G11C11/417

    Abstract: The memory cell (10) comprises two inverter circuits (14,16) interconnected between the data nodes (N1,N2) so to form a memory circuit (12), two programming transistors (28,30) for implementing an irreversible degradation of the gate oxide layers of transistors (18,18'), and two transistors (32,34) for implementing the functioning of the memory cell after programming. Each inverter circuit (14,16) comprises supplementary MOS transistors (18,20;18',20') connected in series between a supply voltage source (VDD) and the ground circuit (22). Each inverter circuit comprises a p-MOS transistor (18,18') and an n-MOS transistor (20,20'), and the data nodes (N1,N2) are formed between the two transistors, n-MOS and p-MOS. The degraded MOS transistor is a transistor with thin gate oxide layer (GO1). The oxide layer is degraded at least locally so to obtain a variation of current through the transistor at the time of reading the cell. The programming transistors (28,30), or the diodes, are connected between the programming control line (PROG) and the transistors of the inverter circuits. The n-MOS programming transistors (28,30) ensure a selective connection of the gates of the transistors (18,18') to a programming voltage (VREF) at a level sufficient to cause the degradation of the gate oxide layers of the transistors. The inverter circuits are interconnected by the intermediary of a n-MOS transistor (32,34) connected to the control line (SRAM) of functioning the cell as the SRAM cell. The drain and the source electrodes of the transistors (32,34) are connected to the gates of the transistors of the inverter circuits.

    Voltage raising electronic circuit implemented by CMOS technology, comprising voltage divider connected to upper half-stage of output
    40.
    发明专利
    Voltage raising electronic circuit implemented by CMOS technology, comprising voltage divider connected to upper half-stage of output 未知

    公开(公告)号：FR2787921A1

    公开(公告)日：2000-06-30

    申请号：FR9816581

    申请日：1998-12-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： CANDELIER PHILIPPE

    IPC: H01L27/092 ,  H03K17/10

    Abstract: The integrated circuit implemented by CMOS (Complementary Metal-Oxide-Semiconductor) technology comprises transistors of p-type and n-type conductivity, and is designed to receive an input signal (Vin) at the level of CMOS logic circuit voltage (Vdd), and to deliver an output logic signal (Vout) of a higher amplitude (HV), e.g. double or treble the input voltage. The circuit comprises the means for limiting the voltage between two connections of each transistor of p-type conductivity to that near the level of CMOS logic circuit, and the means for enabling the transistors of n-type conductivity to support the voltage of higher amplitude. The circuit comprises a voltage divider (1) with outputs (2,2') for voltages lower than the higher voltage (HV) on line (5) connected to the upper half-stage (3), which is in series with the lower half-stage (4) of the output. The transistors of p-type conductivity are implemented with n-type wells, the well of each transistor is individually connected to its source. The transistors of n-type conductivity are asymmetric, and the drains are implemented within wells of the same type conductivity channel. The voltage divider (1) contains a number of transistors of p-type conductivity connected in series and as diodes between the higher voltage supply terminal (5) and the ground (6), where the number of transistors is approximately equal to the ratio of the higher voltage (HV) to the CMOS voltage (Vdd). The output stages (3,4) comprises at least at least two parallel branches with MOS transistors of p-type conductivity, the number of transistors of p-type conductivity is the same as in the voltage divider, where at least one transistor in each branch has the gate connected to the fractional output of the voltage divider; each branch contains a unique transistor, asymmetric and of n-type conductivity, where the drain of such transistor is connected to the output terminal (7) delivering voltage (Vout). The circuit also comprises an inverter of CMOS type connected between one output (2,2') of the divider (1) and the ground (6), and delivering voltage (Vin) approximately equal to the CMOS supply level, and inverted voltage (NVin). In the second embodiment, the circuit for trebling the input voltage contains secondary parallel branches, each containing two p-type transistors and one asymmetric n-type transistor connected in series.

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