公开(公告)号：DE69816032D1

公开(公告)日：2003-08-07

申请号：DE69816032

申请日：1998-04-30

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO

IPC: G11C5/14 ,  G11C16/10 ,  G11C16/00 ,  G11C16/06

Abstract: Upon unwanted interruption of programming, the control logic unit (2) of the memory (1) controls writing of the data that would otherwise be lost and its address, in an appropriate backup memory location (39). To this end, the backup memory location (39) is maintained erased, such as to allow immediate writing of the data and its address, in case of interruption of programming. To guarantee functioning even in the absence of an external supply, appropriate charge accumulators (61) are provided, which can guarantee availability of a write-only cycle. As soon as a voltage drop is detected, the operations in progress are interrupted, and the backup operations for the data being programmed are activated; when the memory (1) is switched on again, it is verified whether an interruption of the writing cycle has previously occurred, and thus the data saved can be recovered into the main memory.

公开(公告)号：DE69325809D1

公开(公告)日：1999-09-02

申请号：DE69325809

申请日：1993-11-24

Applicant: ST MICROELECTRONICS SRL

Inventor： BALDI LIVIO ,  PIO FEDERICO

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: A method for supplying negative programming voltages to non-volatile memory cells in a non-volatile memory device provides for charging a capacitor (C;C1-Cn) to a positive high voltage by connecting, through first switching means (TX,TY;TE1-TEn,TF1-TFn), a first plate (A;A1-An) of the capacitor (C;C1-Cn) to a positive high-voltage supply (Vpp) and connecting, through second switching means (TB;TZ;TD1-TDn), a second plate (B;B';B1-Bn) of the capacitor (C;C1-Cn), which is also operatively connected to the control gate of at least one memory cell, to a reference voltage supply (GND), and for successively connecting, through said first switching means (TX,TY;TE1-TEn,TF1-TFn) the first plate (A;A1-An) of the capacitor (C;C1-Cn) to the reference voltage supply (GND) and disconnecting the second plate (B;B';B1-Bn) of the capacitor (C;C1-Cn) from the reference voltage supply (GND) to obtain a negative voltage on said second plate (B;B';B1-Bn) voltage.

公开(公告)号：DE602005018738D1

公开(公告)日：2010-02-25

申请号：DE602005018738

申请日：2005-03-03

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  BOLANDRINA EFREM ,  VIMERCATI DANIELE

IPC: G11C11/56 ,  G11C16/28

公开(公告)号：DE60140039D1

公开(公告)日：2009-11-12

申请号：DE60140039

申请日：2001-02-05

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO

IPC: G11C16/16

Abstract: A method (t1c-t9c) of erasing a flash memory (300) integrated in a chip of semiconductor material (175) and comprising at least one matrix (105) of cells (Mhk) with a plurality of rows and a plurality of columns made in at least one insulated body (165j), the cells of each row being connected to a corresponding word line (WLh); the method includes the step (t2c-t1c) of applying a single erasing pulse relative to a selected single one of the at least one body to a selected subset of the word lines for erasing the cells of each corresponding row made in the selected body with no intermediate check of the completion of the erasure.

公开(公告)号：DE69838023D1

公开(公告)日：2007-08-16

申请号：DE69838023

申请日：1998-07-30

Applicant: ST MICROELECTRONICS SRL

Inventor： DALLA LIBERA GIOVANNA ,  PIO FEDERICO

IPC: H01L27/115 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/423 ,  H01L29/788

Abstract: The invention relates to non-volatile memory structure integrated on a semiconductor substrate and including a plurality of memory cells (1) each comprising a floating gate transistor having an active area (9) and source/drain (16, 17) regions as well as a control gate coupled to the floating gate, the floating gate transistor being serially connected to a selection transistor. According to the invention a contact (7) is provided on the control gate over the active area (9). The contact is substantially aligned to the central portion of the active area but may even be realized over double-poly wings (18, 19) of the gate region located asymmetrically with respect to the active area.

公开(公告)号：DE60200715D1

公开(公告)日：2004-08-12

申请号：DE60200715

申请日：2002-02-20

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO

IPC: G11C8/08 ,  G11C8/10 ,  G11C16/08 ,  G11C16/16

Abstract: A word line selector for selecting word lines (WL1 - WLm) of an array (101) of semiconductor memory cells (MC) formed in a doped semiconductor region (103) of a semiconductor substrate (107) comprises a plurality of word line drivers (3011,3012) responsive to word line selection signals (WLSA1,WLSa2). Each word line driver is associated with a respective word line for driving the word line to prescribed word line electric potentials, depending on an operation to be conducted on the array of memory cells, in accordance with the word line selection signal. A plurality of distinct doped semiconductor well structures (115a - 115p) is provided in the semiconductor substrate. Each doped semiconductor well structure accommodates a respective group (113a - 113p) of at least one word line driver associated with a respective group (WL1-WLh,WLk-WLm) of at least one word line. The different doped semiconductor well structures can thus be biased independently of each other to respective semiconductor well bias potentials, so that the word line potentials of word lines of different groups need not be correlated.

公开(公告)号：ITMI981449A1

公开(公告)日：1999-12-25

申请号：ITMI981449

申请日：1998-06-25

Applicant: ST MICROELECTRONICS SRL

Inventor： CREMONESI CARLO ,  ZATELLI NICOLA ,  PIO FEDERICO

IPC: H01L21/8247 ,  H01L27/115

Abstract: Process for manufacturing a non-volatile memory with memory cells arranged in rows and columns in a matrix structure, with source lines extending in parallel with and intercalated to said rows, the cells including MOS transistors having a floating gate and a control gate respectively formed in a first and a second polysilicon layers superimposed, the process including a first step of definition of regions of active area covered by a layer of thin oxide and delimited by regions of field oxide, a second step of deposition of the first polysilicon layer, a third step of etch of the first polysilicon layer through a first mask to separate the floating gates of cells belonging to a same row of the matrix, a fourth step of deposition of an intermediate dielectric layer and of the second polysilicon layer, a fifth step of definition of the rows through self-aligned selective etch of said second polysilicon layer, of the intermediate dielectric layer and of the first polysilicon layer, the self-aligned selective etch determining in the source lines excavations in correspondence of regions in which the first polysilicon layer has been removed during the third step, and a sixth step of dopant introduction in the regions of active area for the formation of regions of source and drain of the cells. Before the fourth step a selective introduction of dopant is provided in correspondence of regions of the common source lines in which the excavations will be formed, for the formation of doped regions deeper than the excavations.

公开(公告)号：DE69325505T2

公开(公告)日：1999-10-28

申请号：DE69325505

申请日：1993-02-19

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  RIVA CARLO

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  G11C16/04

公开(公告)号：DE69325505D1

公开(公告)日：1999-08-05

申请号：DE69325505

申请日：1993-02-19

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  RIVA CARLO

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  G11C16/04

公开(公告)号：DE69932703T2

公开(公告)日：2007-09-06

申请号：DE69932703

申请日：1999-04-21

Applicant: ST MICROELECTRONICS SRL

Inventor： GOMIERO ENRICO ,  PIO FEDERICO ,  ZULIANI PAOLA

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/12

Abstract: A non-volatile memory portion (1) includes a matrix of memory cells (2) comprising rows as the wordlines (WL) and columns as the bit-lines (BL). Control circuitry (3) includes a program voltage generator (7), an adjuster (25) of the voltage (Vst) applied to the matrix rows, a first adjuster (4) of an erase voltage (VppE) and a second adjuster (5) of a write voltage (VppW). The program voltage during the erasing phase is set higher than during the writing phase. An independent claim is also included for a process of fabricating a semiconductor non-volatile memory including forming a bit-switch element inside a well and a byte switch element directly in the substrate.