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31.发明专利
公开(公告)号：IT1404188B1
公开(公告)日：2013-11-15
申请号：ITMI20110309
申请日：2011-02-28
Applicant: ST MICROELECTRONICS SRL
Inventor： MICCICHE MARIO , MAMMOLITI FRANCESCO , UCCIARDELLO CARMELO , CONTE ANTONINO
IPC: H02M3/07
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32.发明专利
公开(公告)号：ITTO20120192A1
公开(公告)日：2013-09-06
申请号：ITTO20120192
申请日：2012-03-05
Applicant: ST MICROELECTRONICS SRL
Inventor： CONTE ANTONINO , DI MARTINO ALBERTO JOSE , GRANDE FRANCESCA , SIGNORELLO ALFREDO
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公开(公告)号：DE602004003465D1
公开(公告)日：2007-01-11
申请号：DE602004003465
申请日：2004-02-19
Applicant: ST MICROELECTRONICS SA , ST MICROELECTRONICS SRL
Inventor： DEMANGE NICOLAS , CONTE ANTONINO , PRECISO SALVATORE , SIGNORELLO ALFREDO
Abstract: A sensing circuit (120) for sensing currents, including at least one sense amplifier (122), comprising: a measure circuit branch (132i), having a measure node for receiving an input current (Ic) to be sensed, for converting the input current into a corresponding input voltage (V-); at least one comparison circuit branch (132o), having a comparison node for receiving a comparison current (Igs), for converting the comparison current into a corresponding comparison voltage (V+); and at least one voltage comparator (140) for comparing the input and comparison voltages, and means (N3s,135; N3s,135';N3s,135" ) for generating the comparison current based on a reference current (Ir), said means comprising: at least one voltage generator (135;135';135'') for receiving the reference current and for generating a corresponding sense amplifier biasing voltage (Vsab); and means (N3s) for converting the sense amplifier biasing voltage into the comparison current. The at least one voltage generator includes a first circuit branch (232i), having a first node for receiving the reference current, for converting the reference current into a corresponding reference voltage (Vref), a second circuit branch (232o), having a second node for receiving a regulation current (Ii), in current mirror configuration with the first circuit branch for mirroring a current (Img) corresponding to the reference current, the second circuit branch generating by conversion a non-regulated voltage (Vgen) corresponding to the mirrored current and to the regulation current, and voltage regulator means (N3g,240) receiving the reference voltage and the non-regulated voltage for regulating the sense amplifier biasing voltage by controlling the non-regulated voltage through the regulation current.
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公开(公告)号：DE60123925D1
公开(公告)日：2006-11-30
申请号：DE60123925
申请日：2001-04-27
Applicant: ST MICROELECTRONICS SRL
Inventor： CONTE ANTONINO , CONCEPITO ORESTE
Abstract: The present invention relates to a current reference circuit for low supply voltages comprising a current source (I), connected at a side to a supply voltage (Vcc) and to the other side to a series (21) composed by a resistance (R2) and diode (D1), said diode (D1) having the cathode electrode connected to the ground and the anode electrode connected with said resistance (R2), characterized in that to comprise also a transistor (M1) and an operational amplifier (OP), said transistor (M1) having the gate electrode connected to the output of said operational amplifier (OP), said transistor (M1) having the source electrode connected to the ground, said transistor (M1) having the drain electrode connected to the positive electrode of said operational amplifier (OP), with said current source (I) and with said series (21), said operational amplifier (OP) having the negative electrode connected to a band gap reference voltage (VBG).
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公开(公告)号：ITMI20042052A1
公开(公告)日：2005-01-28
申请号：ITMI20042052
申请日：2004-10-28
Applicant: ST MICROELECTRONICS SRL
Inventor： CONTE ANTONINO , DI MARTINO ALBERTO
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Patent Agency Ranking
公开(公告)号：ITVA20020020A1
公开(公告)日：2003-09-04
申请号：ITVA20020020
申请日：2002-03-04
Applicant: ST MICROELECTRONICS SRL
Inventor： CASTALDO ENRICO , CONTE ANTONINO
IPC: H02M3/07
Abstract: A circuit for regulating an output voltage of a charge pump includes a regulator connected to an output of the charge pump. The regulator includes a voltage divider for dividing the output voltage. A filter has a first input for receiving the divided output voltage, a second input for receiving a control signal, and an output for providing a filtered divided output voltage. A comparator has a first input for receiving the divided output voltage, a second input for receiving a reference voltage, a third input for receiving the filtered divided output voltage, and an output for providing a digital signal based upon a comparison of the divided output signal, the reference voltage and the filtered divided output voltage. A logic control circuit has a first input for receiving a clock signal, a second input for receiving the digital signal from the comparator, and an output for providing a timing signal. A phase generator circuit has an input for receiving the timing signal from the logic control circuit for generating control phases for the charge pump.
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公开(公告)号：ITMI20002763A1
公开(公告)日：2002-06-20
申请号：ITMI20002763
申请日：2000-12-20
Applicant: ST MICROELECTRONICS SRL
Inventor： CONTE ANTONINO , LA ROCCA ROSANNA MARIA , MATRANGA GIOVANNI
IPC: G11C16/28
Abstract: A reading circuit is provided for reading a memory cell. The reading circuit includes a reference current source, a memory cell biased between its first and second terminals at a predetermined voltage, comparison means for comparing a current flowing in the memory cell with the reference current, and a control gate voltage source coupled to a third terminal of the memory cell. The control gate voltage source includes a virgin memory cell that is biased between two terminals with a voltage of equal value to the biasing voltage of the memory cell. The control gate voltage source produces a control gate voltage at another terminal of the virgin memory cell. In one preferred embodiment, the memory cell and the virgin memory cell are EEPROM cells.
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公开(公告)号：IT202100030134A1
公开(公告)日：2023-05-29
申请号：IT202100030134
申请日：2021-11-29
Applicant: ST MICROELECTRONICS SRL
Inventor： MACCARRONE AGATINO MASSIMO , CONTE ANTONINO , TOMAIUOLO FRANCESCO , PISASALE MICHELANGELO , RUTA MARCO
IPC: H03M20060101
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公开(公告)号：FR3113327A1
公开(公告)日：2022-02-11
申请号：FR2008286
申请日：2020-08-05
Applicant: ST MICROELECTRONICS ROUSSET , ST MICROELECTRONICS SRL
Inventor： LA ROSA FRANCESCO , CONTE ANTONINO
Abstract: Le procédé de calcul convolutif (CNVL) comprend le fait de programmer des transistors à grille flottante (FGT) appartenant à des cellules mémoire non volatile (NVM) pour les mettre à des tensions de seuil multiniveaux (MLTLVL) selon des facteurs de pondération (W11-Wnm) d’un opérateur matriciel convolutif (MTXOP). Le calcul comprend le fait d’exécuter une séquence de multiplication et accumulation (MACi) pendant une opération de lecture (SNS) de cellules mémoire (NVMij), le temps (T) écoulé pour que chaque cellule mémoire devienne conductrice en réponse à un signal de commande en rampe de tension (VRMP) fournissant la valeur de chaque produit de valeurs d’entrée (A1…An) par un facteur de pondération respectif (Wi1…Win), les valeurs des produits étant accumulées avec des valeurs de sortie correspondantes (Bi). Figure pour l’abrégé : Fig 3
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公开(公告)号：FR3113326A1
公开(公告)日：2022-02-11
申请号：FR2008327
申请日：2020-08-06
Applicant: ST MICROELECTRONICS ROUSSET , ST MICROELECTRONICS SRL
Inventor： CONTE ANTONINO , LA ROSA FRANCESCO
Abstract: Le circuit intégré pour le calcul convolutif (CNVL) comprend une matrice (ARR) de points mémoires non volatils (MPTij) comprenant chacun une cellule mémoire résistive à changement de phase (PCMij) couplée à une ligne de bit (BLj), et un transistor bipolaire de sélection (BJTij) couplé en série à la cellule et ayant une borne de base reliée à une ligne de mot (WLi), un circuit convertisseur d’entrée (INCVRT) configuré pour recevoir et convertir des valeurs d’entrée (A1-A4) en signaux de tension (V1-V4) et pour appliquer successivement les signaux de tension (V1-V4) sur des lignes de bit sélectionnées (BL1-BL4) sur des intervalles de temps respectifs (t1-t4), et un circuit convertisseur de sortie (OUTCVRT) configuré pour intégrer sur les intervalles de temps successifs (t1-t4) les courants de lecture (IWL) résultant des signaux de tension (V1-V4) qui polarisent les cellules mémoires résistives à changement de phase respectives (PCMij) et circulant dans des lignes de mots sélectionnées, et pour convertir les courants de lecture intégrés (IWL) en valeurs de sortie (Bi). Figure de l’abrégé : Fig 4
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