-
公开(公告)号:IT1236797B
公开(公告)日:1993-04-02
申请号:IT2242889
申请日:1989-11-17
Applicant: ST MICROELECTRONICS SRL
Inventor: FERLA GIUSEPPE , PALARA SERGIO
IPC: H01L21/331 , H01L29/73 , H01L21/822 , H01L27/02 , H01L27/04 , H01L27/06 , H01L27/082 , H01L29/732 , H01L
Abstract: The monolithic vertical-type semiconductor power device comprises an N+ type substrate (1) over which there is superimposed an N- type epitaxial layer (2) in which there is obtained aP type insulation pocket (3). Such pocket contains N type regions (4, 15) and P type regions (8) which in turn contain N+ type regions (11, 12; 13; 14) and of P type regions (6, 7, 9, 10) which define circuit components (T1, T2, T5) of the device. Insulation pocket (3) is wholly covered by a first metallisation (21, 30) connected to ground. Such metallisation (21, 30) is in turn protected by a layer of insulating material (18) suitable for allowing the crossing of metal tracks (20) or of a second metallisation (31) for the connection of the different components.
-
公开(公告)号:DE602005025846D1
公开(公告)日:2011-02-24
申请号:DE602005025846
申请日:2005-11-18
Applicant: ST MICROELECTRONICS SRL
Inventor: MAGRI ANGELO , FRISINA FERRUCCIO , FERLA GIUSEPPE
IPC: H01L29/78 , H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49
-
公开(公告)号:DE69938541D1
公开(公告)日:2008-05-29
申请号:DE69938541
申请日:1999-06-03
Applicant: ST MICROELECTRONICS SRL
Inventor: SCHILLACI ANTONINO , GRIMALDI ANTONIO , FERLA GIUSEPPE
-
公开(公告)号:DE69533134D1
公开(公告)日:2004-07-15
申请号:DE69533134
申请日:1995-10-30
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor: MAGRI ANGELO , FRISINA FERRUCCIO , FERLA GIUSEPPE
IPC: H01L21/336 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/78 , H01L29/739
Abstract: A MOS technology power device comprises a plurality of elementary functional units which contribute for respective fractions to an overall current of the power device and which are formed in a semiconductor material layer (2) of a first conductivity type. Each elementary functional unit comprises a body region (3) of a second conductivity type formed in the semiconductor material layer (2), the body region (3) having the form of a body stripe (3) elongated in a longitudinal direction on a surface of the semiconductor material layer (2). Each body stripe (3) includes at least one source portion (60) doped with dopants of the first conductivity type which is intercalated with a body portion (40) of the body stripe (3) wherein no dopants of the first conductivity type are provided.
-
公开(公告)号:DE69910736D1
公开(公告)日:2003-10-02
申请号:DE69910736
申请日:1999-06-03
Applicant: ST MICROELECTRONICS SRL
Inventor: GRIMALDI ANTONIO , SCHILLACI ANTONINO , FERLA GIUSEPPE
-
公开(公告)号:DE69429913D1
公开(公告)日:2002-03-28
申请号:DE69429913
申请日:1994-06-23
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor: FERLA GIUSEPPE , FRISINA FERRUCCIO
IPC: H01L29/78 , H01L21/336 , H01L29/10 , H01L29/739
-
公开(公告)号:DE69428894D1
公开(公告)日:2001-12-06
申请号:DE69428894
申请日:1994-08-02
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor: FERLA GIUSEPPE , FRISINA FERRUCCIO
IPC: H01L29/78 , H01L29/739
Abstract: A power device integrated structure comprises a semiconductor substrate (5) of a first conductivity type, a semiconductor layer (3,4) of a second conductivity type superimposed over said substrate (5), a plurality of first doped regions (2) of the first conductivity type formed in the semiconductor layer (3,4), and a respective plurality of second doped regions (11) of the second conductivity type formed inside the first doped regions (2); the power device comprises: a power MOSFET (M) having a first electrode region represented by the second doped regions (11) and a second electrode region represented by the semiconductor layer (3,4); a first bipolar junction transistor (T2) having an emitter, a base and a collector respectively represented by the substrate (5), the semiconductor layer (3,4) and the first doped regions (2); and a second bipolar junction transistor (T1) having an emitter, a base and a collector respectively represented by the second doped regions (11), the first doped regions (2) and the semiconductor layer (3,4); the doping profiles of the semiconductor substrate (5), the semiconductor layer (3,4), the first doped regions (2) and the second doped regions (11) are such that the first and second bipolar junction transistors (T2,T1) have respective first and second common base current gains sufficiently high to cause said bipolar junction transistors to be biased in the high injection region, so that carriers are injected from the substrate (5) into the semiconductor layer (3,4) and from the second doped regions (11), through the first doped regions (2), into the semiconductor layer (3,4), the conductivity of the semiconductor layer (3,4) is thus modulated not only by the injection of minority carriers from the substrate (5), but also by majority carriers injected from the doped regions (11) into the first doped regions (2) and collected by the semiconductor layer (3,4). The first and second common base current gains summed are less than unity to prevent a parasitic thyristor from triggering on. The power device functions as an IGBT, having a reduced on-state voltage.
-
公开(公告)号:DE69515876D1
公开(公告)日:2000-04-27
申请号:DE69515876
申请日:1995-11-06
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor: FRISINA FERRUCCIO , FERLA GIUSEPPE , RINAUDO SALVATORE
IPC: H01L21/336 , H01L29/08 , H01L29/78
-
公开(公告)号:DE69033271T2
公开(公告)日:2000-02-17
申请号:DE69033271
申请日:1990-02-20
Applicant: ST MICROELECTRONICS SRL
Inventor: SANTANGELO ANTONELLO , MAGRO CARMELO , FERLA GIUSEPPE , LANZA PAOLO
IPC: H01L21/265 , H01L21/28 , H01L21/285 , H01L21/329 , H01L21/768 , H01L21/60
Abstract: The process consists of enrichment of the surface of the semiconductor on which the contact is to be formed, by ion implantation of dopant, followed by deposition of a metal film on the implanted surface and then by thermal annealing at a temperature considerably lower than 500 DEG C and for a period considerably shorter than 60 minutes.
-
公开(公告)号:DE69033271D1
公开(公告)日:1999-10-07
申请号:DE69033271
申请日:1990-02-20
Applicant: ST MICROELECTRONICS SRL
Inventor: SANTANGELO ANTONELLO , MAGRO CARMELO , FERLA GIUSEPPE , LANZA PAOLO
IPC: H01L21/265 , H01L21/28 , H01L21/285 , H01L21/329 , H01L21/768 , H01L21/60
Abstract: The process consists of enrichment of the surface of the semiconductor on which the contact is to be formed, by ion implantation of dopant, followed by deposition of a metal film on the implanted surface and then by thermal annealing at a temperature considerably lower than 500 DEG C and for a period considerably shorter than 60 minutes.
-
-
-
-
-
-
-
-
-