公开(公告)号：DE69421071D1

公开(公告)日：1999-11-11

申请号：DE69421071

申请日：1994-05-23

Applicant: ST MICROELECTRONICS SRL

Inventor： ZUFFADA MAURIZIO ,  GADDUCCI PAOLO ,  MOLONEY DAVID ,  ALINI ROBERTO

IPC: G11B5/09 ,  G11B20/10

Abstract: The device comprises a variable-gain input amplifier (21), a low-pass analog filter (22), a transversal analog filter (23) and two distinct and parallel sampling channels (24, 34) interposed between the transversal analog filter (23) and an RLL-NRZ decoder (25). The two sampling channels (24, 34) comprise, each of them, an analog-digital converter (26, 36) and a Viterbi detector (27, 37) arranged in succession one after the other and operating according to sampling sequences that alternate with one another.

公开(公告)号：DE69325888D1

公开(公告)日：1999-09-09

申请号：DE69325888

申请日：1993-02-26

Applicant: ST MICROELECTRONICS SRL

Inventor： ALINI ROBERTO ,  MOLONEY DAVID ,  GORNATI SILVANO ,  PORTALURI SALVATORE

IPC: G06F13/38 ,  G11C5/00

公开(公告)号：IT9021816D0

公开(公告)日：1990-10-22

申请号：IT2181690

申请日：1990-10-22

Applicant: ST MICROELECTRONICS SRL

Inventor： MOLONEY DAVID ,  ZUFFADA MAURIZIO ,  VAI GIANFRANCO ,  SACCHI FABRIZIO

IPC: G06F1/24 ,  G06F7/00 ,  G06F11/00 ,  G06F11/08 ,  G06F11/28 ,  G06F11/30

Abstract: Finite-state machine for reliable computing and adjustment systems, which comprises a combinatorial logic (10) connected to a status memory (11) by means of connections which carry future state signals (12) and of connections which carry current state signals (13). The combinatorial logic (10) comprises input terminals (14) for input signals which are external to the finite-state machine and output terminals (15) for output signals generated by the combinatorial logic (10). The finite-state machine furthermore comprises means for comparing the future state signals (12) to at least one reference level (16); the comparison means set an error signal (18) toward means for resetting the finite-state machine and/or the system which includes it.

公开(公告)号：IT9020728D0

公开(公告)日：1990-06-22

申请号：IT2072890

申请日：1990-06-22

Applicant: ST MICROELECTRONICS SRL

Inventor： MOLONEY DAVID ,  VAI GIANFRANCO ,  ZUFFADA MAURIZIO ,  BETTI GIORGIO

IPC: H03K19/0175 ,  H03K19/094 ,  H03K19/0948

Abstract: The tristate output gate structure particularly for CMOS integrated circuits comprises an enable terminal (30) receiving an enable signal and an input terminal (31) receiving an input signal, which connects, through signal switching means (38), an output terminal (32) to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor (33) through signal inverting means (35,37) and to the gate terminal of a second N-channel transistor (34). The output terminal (32) is electrically connected to the drain terminals of the first and second transistors (33,34). The first and second transistors (33,34) electrically insulate the output terminal (32) from the input terminal (31).