公开(公告)号：DE69325277T2

公开(公告)日：2000-01-20

申请号：DE69325277

申请日：1993-12-31

Applicant: ST MICROELECTRONICS SRL

Inventor： PADOAN SILVIA ,  OLIVO MARCO ,  GOLLA CARLA

IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30

Abstract: A circuit for detecting a threshold voltage in storage devices integrated to a semiconductor, for which a power supply above a certain value is provided, is of the type which comprises a comparator (3) connected between a voltage supply line (2) and a signal ground (GND) and having a first or reference input (I1) and a second or signal input (I2), and comprises a generator (8) of a stable voltage reference (RIF) having an output connected to the first input (I1) and a divider (9) of a supply voltage (Vdd) connected to the second input (I2) of the comparator (3). A circuit means is arranged to feed the voltage line (2) with the higher of the supply voltage (Vdd) value and the value of a programming voltage (Vpp) of the storage device.

公开(公告)号：DE69326154D1

公开(公告)日：1999-09-30

申请号：DE69326154

申请日：1993-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  PADOAN SILVIA

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G06F11/20

Abstract: An integrated circuit for the programming of a memory cell in a non-volatile memory register, said memory cell comprising at least one programmable non-volatile memory element (TF;TF0,TF1) having a cotrol electrode and a supply electrode and being suitable to store one bit of information and a load circuit (LC;T0-T3) associated to said memory element (TF;TF0,TF1) to read the information stored therein, comprises switching means (TS;T4,T5), connected in series between the supply electrode of said at least one memory element (TF;TF0,TF1) and a respective data line (A;A,AN) carrying a datum to be programmed into said memory element (TF;TF0,TF1); the switching means are controlled by a signal (7) which determines the switching means (TS;T4,T5) to electrically connect the memory element (TF;TF0,TF1) to the data line (A;A,AN) when the memory cell of the non-volatile memory register is to be programmed.

公开(公告)号：DE69325458D1

公开(公告)日：1999-07-29

申请号：DE69325458

申请日：1993-12-31

Applicant: ST MICROELECTRONICS SRL

Inventor： OLIVO MARCO ,  PADOAN SILVIA

IPC: G06F1/24 ,  G11C17/00 ,  G11C16/06 ,  G11C16/30

Abstract: A method for generating a reset signal in an electrically programmable non-volatile storage device (1) of a type which comprises a matrix (2) of memory cells and a control logic portion (3) being supplied a supply voltage (Vcc) and a programming voltage (Vpp), and a threshold detection circuit (5) adapted to detect a decrease in the supply voltage (Vcc), provides for the signal applied to the control logic (3) to be obtained as a change-over function between the output signal from the threshold detector (5) and a reset signal (POR) generated during the power-on transient of the device.

公开(公告)号：DE69428423D1

公开(公告)日：2001-10-31

申请号：DE69428423

申请日：1994-02-21

Applicant: ST MICROELECTRONICS SRL

Inventor： GOLLA CARLA ,  PADOAN SILVIA ,  OLIVO MARCO

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/14 ,  G11C16/16

Abstract: A regulating circuit for discharging non-volatile memory cells (5) in an electrically programmable memory device, of the type which comprises: at least one switch connected between a programming voltage reference (VPP) and a line (SCR) shared by the source terminals of the transistors forming said memory cells (5), and at least one discharge connection between said common line (SCR) to the source terminals and a ground voltage reference (GND), further comprises a second connection to ground of the line (SCR) in which a current (Is) generator (G) is connected and a normally open switch (I1). Also provided is a logic circuit (3) connected to the line (SRC) to compare the voltage value present on the latter with a predetermined value, and to output a control signal for causing the switch (I1) to make. This solution allows a slow discharging phase of the line (SRC) to be effected at the end of the erasing phase.

公开(公告)号：DE69328623D1

公开(公告)日：2000-06-15

申请号：DE69328623

申请日：1993-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： PADOAN SILVIA ,  GOLLA CARLA

IPC: H01L27/04 ,  G05F3/24 ,  H01L21/822

公开(公告)号：DE69421266T2

公开(公告)日：2000-05-18

申请号：DE69421266

申请日：1994-02-18

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  PADOAN SILVIA ,  GOLLA CARLA MARIA ,  MACCARRONE MARCO ,  OLIVO MARCO

IPC: G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C7/00 ,  G11C16/06

Abstract: The circuit (1) comprises a section (2) generating a pulse signal (ATD) for asynchronously enabling the read phases; a section (4) generating precharge (PC) and detecting (DET) signals of adjustable duration, for controlling data reading from the memory (104) and data supply to the output buffers (106); a section (5) generating a noise suppressing signal (N) for freezing the data in the output buffers during loading into the output circuits, and the duration of which is exactly equal to the propagation time of the data to the output circuits of the memory, as determined by propagating a data simulating signal (SP) in an out-like circuit (33); a section (6) generating a loading signal (L), the duration of which may be equal to that of the noise suppressing signal (N) or extended by an extension circuit (51) in the event the array presents slower elements which may thus be read; and a section (7) generating a circuit reset signal (END).

公开(公告)号：DE69421266D1

公开(公告)日：1999-11-25

申请号：DE69421266

申请日：1994-02-18

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  PADOAN SILVIA ,  GOLLA CARLA MARIA ,  MACCARRONE MARCO ,  OLIVO MARCO

IPC: G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C7/00 ,  G11C16/06

Abstract: The circuit (1) comprises a section (2) generating a pulse signal (ATD) for asynchronously enabling the read phases; a section (4) generating precharge (PC) and detecting (DET) signals of adjustable duration, for controlling data reading from the memory (104) and data supply to the output buffers (106); a section (5) generating a noise suppressing signal (N) for freezing the data in the output buffers during loading into the output circuits, and the duration of which is exactly equal to the propagation time of the data to the output circuits of the memory, as determined by propagating a data simulating signal (SP) in an out-like circuit (33); a section (6) generating a loading signal (L), the duration of which may be equal to that of the noise suppressing signal (N) or extended by an extension circuit (51) in the event the array presents slower elements which may thus be read; and a section (7) generating a circuit reset signal (END).

公开(公告)号：DE69325277D1

公开(公告)日：1999-07-15

申请号：DE69325277

申请日：1993-12-31

Applicant: ST MICROELECTRONICS SRL

Inventor： PADOAN SILVIA ,  OLIVO MARCO ,  GOLLA CARLA

IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30

Abstract: A circuit for detecting a threshold voltage in storage devices integrated to a semiconductor, for which a power supply above a certain value is provided, is of the type which comprises a comparator (3) connected between a voltage supply line (2) and a signal ground (GND) and having a first or reference input (I1) and a second or signal input (I2), and comprises a generator (8) of a stable voltage reference (RIF) having an output connected to the first input (I1) and a divider (9) of a supply voltage (Vdd) connected to the second input (I2) of the comparator (3). A circuit means is arranged to feed the voltage line (2) with the higher of the supply voltage (Vdd) value and the value of a programming voltage (Vpp) of the storage device.