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    31.
    发明专利
    未知

    公开(公告)号：DE60039027D1

    公开(公告)日：2008-07-10

    申请号：DE60039027

    申请日：2000-03-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO ,  MONTANARO MASSIMO ,  ODDONE GIORGIO

    IPC: G11C16/12

    Abstract: The integrated device (100) comprises a PMOS transistor (101) and a voltage selector (1) having an output (6g) connected to the bulk terminal (101d) of the PMOS transistor (101). The voltage selector (1) comprises an input stage (2) supplying (2c) a supply voltage (Vdd) or a programming voltage (Vpp) according to whether the device (100) is in a reading step or in a programming step; a comparator (3) connected to the output (2c) of the input stage (2), receiving a boosted voltage (Vboost), and generating (3g) a first control signal (OC), the state whereof depends upon the comparison of the voltages at the inputs of the comparator (3); a logic circuit (4) connected to the output (3g) of the comparator (3) and generating a second control signal (VDDIS), the state whereof depends upon the state of the first control signal (OC) and of a third-level signal (VTL); and a switching circuit (6) controlled by the first control signal (OC), by the second control signal (VDDIS), and by the third-level signal (VTL) and supplying (6g) each time the highest among the supply voltage (Vdd), the boosted voltage (Vboost), and the programming voltage (Vpp).

    36.
    发明专利
    未知

    公开(公告)号：DE69635105D1

    公开(公告)日：2005-09-29

    申请号：DE69635105

    申请日：1996-01-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO

    IPC: G11C11/41 ,  G06F12/16 ,  G11C11/56 ,  G11C11/00

    Abstract: The present invention relates to a memory circuit of the multi-level type, i.e. a memory circuit comprising a plurality (MTX) of memory elements, each adapted to store more than one binary information unit, wherein the memory elements are utilized for storing a number of binary information units tied to an acceptable error rate for a particular application: typically, one bit where a low error rate is sought, and two bits where a higher error rate can be accepted.

    38.
    发明专利
    未知

    公开(公告)号：DE69531823T2

    公开(公告)日：2004-07-01

    申请号：DE69531823

    申请日：1995-07-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  ROLANDI PAOLO ,  BARCELLA ANTONIO ,  FONTANA MARCO

    IPC: G06F11/20 ,  G11C7/20 ,  H03K3/356 ,  G11C16/06

    Abstract: A latch circuit (1) that is intentionally imbalanced, so that a first output (6) reaches ground voltage and a second output (7) reaches a supply voltage; and a fully static low-consumption fuse circuit the particularity whereof resides in that it comprises the intentionally unbalanced latch circuit (1) and a reversing branch that comprises the fuse to be programmed (6) and is adapted to reverse the operation of the latch circuit, so that in the virgin state the fuse (9) connects the second output (7) of the latch circuit (1) to the ground voltage and connects the first output (6) to the supply voltage.

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