公开(公告)号：EP1535878A1

公开(公告)日：2005-06-01

申请号：EP03425770.9

申请日：2003-11-28

Applicant: STMicroelectronics S.r.l.

Inventor： Barlocchi, Gabriele ,  Mastromatteo, Ubaldo ,  Villa, Flavio Francesco

IPC: B81B3/00 ,  B81B1/00 ,  B01L3/00

CPC classification number: B81C1/00539 ,  B01L3/502707 ,  B01L2200/10 ,  B01L2200/12 ,  B81B2201/051

Abstract: The microreactor has a body (21) of semiconductor material; a channel (25) extending in the body (21) and having walls (25a); a coating layer (34) of insulating material coating the walls (25a) of the channel (25); a diaphragm (26) extending on top of the body (21) and upwardly closing the channel. The diaphragm (26) is formed by a semiconductor layer (28) completely encircling mask portions (22) of insulating material.

Abstract translation: 微型反应器具有半导体材料的本体（21）; 一个通道（25）在所述主体（21）和具有壁（25A）延伸; 绝缘材料涂覆所述通道的壁（25A）（25）的被覆层（34）; 隔膜（26）在所述主体（21）和向上关闭通道的顶部延伸。 隔膜（26）由绝缘材料制成的半导体层（28）完全环绕调用掩模部分（22）形成。

公开(公告)号：EP0856825B1

公开(公告)日：2004-11-17

申请号：EP97830034.1

申请日：1997-01-31

Applicant: STMicroelectronics S.r.l.

Inventor： Mastromatteo, Ubaldo ,  Vigna, Benedetto

IPC: G08B1/00 ,  G01N27/12

CPC classification number: G01N27/12

公开(公告)号：EP1085568B1

公开(公告)日：2004-07-07

申请号：EP99830586.6

申请日：1999-09-17

Applicant: STMicroelectronics S.r.l.

Inventor： Murari, Bruno ,  Mastromatteo, Ubaldo ,  Vigna, Benedetto

IPC: H01L21/60

CPC classification number: H01L24/81 ,  H01L23/345 ,  H01L24/98 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16148 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81234 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2224/05599

公开(公告)号：EP1031736B1

公开(公告)日：2004-04-28

申请号：EP99830107.1

申请日：1999-02-26

Applicant: STMicroelectronics S.r.l.

Inventor： Vigna, Benedetto ,  Mastromatteo, Ubaldo

IPC: F16B1/00

CPC classification number: B81C1/00896

公开(公告)号：EP1225635A3

公开(公告)日：2003-07-16

申请号：EP02001501.2

申请日：2002-01-22

Applicant: STMicroelectronics S.r.l. ,  Hewlett-Packard Company

Inventor： Mastromatteo, Ubaldo

IPC: H01L23/48 ,  H01L25/16 ,  H01L25/065 ,  H01L25/07 ,  B81C3/00

CPC classification number: H01L23/5225 ,  H01L23/481 ,  H01L23/60 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/074 ,  H01L29/0657 ,  H01L2223/6622 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/45099 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: The integrated semiconductor device (1) includes a first chip (4) of semiconductor material having first, high-voltage, regions (12-17) at a first high-value voltage; a second chip (6) of semiconductor material having second high-voltage regions (31, 33) connected to the first voltage; and a third chip (5) of semiconductor material arranged between the first chip and the second chip and having at least one low-voltage region (21) at a second, low-value, voltage. A through connection region (22) is formed in the third chip and is connected to the first and second high-voltage regions; through insulating regions (23-25) surround the through connection region and insulate it from the low-voltage region.

公开(公告)号：EP1312943A1

公开(公告)日：2003-05-21

申请号：EP01830701.7

申请日：2001-11-14

Applicant: STMicroelectronics S.r.l.

Inventor： Mastromatteo, Ubaldo ,  Corona, Pietro ,  Villa, Flavio ,  Barlocchi, Gabriele

IPC: G02B5/08 ,  G02B6/36

CPC classification number: G11B7/1362 ,  G02B5/08 ,  G02B6/4214 ,  G11B7/123 ,  Y10T428/12528

Abstract: Method for manufacturing electromagnetic radiation reflecting devices (23), said method comprising the steps of:

a) providing a silicon substrate (1) defined by at least one first free surface (2),
b) forming on said first surface a layer of protective material provided with an opening which exposes a region of the first free surface (2),
c)etching the region of the free surface (2) by means of an anisotropic agent to remove at least one portion of the substrate and define a second free surface (16) of the substrate inclined in relation to said first surface. Furthermore, said first free surface (2) is parallel to the crystalline planes {110} of silicon substrate and said step c) comprises a progressing step of the anisotropic agent such that the second free surface (16) resulting from the etching step is parallel to the planes {100} of said substrate (1).

Abstract translation: （23）所述的方法包括以下步骤：用于制造电磁辐射反射装置的方法：a）提供一个硅衬底（1）由至少一个第一自由表面（2）定义，b）形成于所述第一表面的保护层 在开口设置有材料暴露第一自由表面（2）的一个区域，c）通过各向异性剂的方式蚀刻所述自由表面（2）的区域，以除去所述基板的至少一个部分并限定第二自由 在倾斜于所述第一表面的基板的表面（16）。 进一步，所述第一自由表面（2）是平行于晶面的硅基板的ä110ü和所述步骤c）包括将所述各向异性剂的进展步骤检查做了第二自由表面（16）从蚀刻步骤产生平行于 所说基片的俯视ä100ü（1）。

公开(公告)号：EP1219565A1

公开(公告)日：2002-07-03

申请号：EP00830867.8

申请日：2000-12-29

Applicant: STMicroelectronics S.r.l.

Inventor： Mastromatteo, Ubaldo

IPC: B81C3/00 ,  H01L21/98 ,  H01L21/60

CPC classification number: B81C1/00238 ,  B81C2201/019 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13144 ,  H01L2224/45144 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05684

Abstract: A process for manufacturing an integrated device (36) comprises the steps of: forming, in a first wafer (1) of semiconductor material, integrated structures (3, 4) including semiconductor regions (10, 12-15, 20) and isolation regions (7, 18); forming, on a second wafer (25) of semiconductor material, interconnection structures (28-30, 32) of a metal material including plug elements (32) having at least one bonding region (34) of a metal material capable of reacting with the semiconductor regions (10, 12-15, 20) of the first wafer (1); and bonding the first and second wafers together by causing the bonding regions (34; 70) of the plug elements (32) to react directly with the semiconductor regions so as to form a metal silicide. Thereby, the metallurgical operations for forming the interconnection structures are completely independent of the operations required for processing silicon, so that there is no interference whatsoever between the two sets of operations. In addition, the areas where the two wafers are made may be separate, and the interconnection structures may be made with materials incompatible with silicon processing, without any risk of contamination.

Abstract translation: 一种用于制造集成器件（36）的方法包括以下步骤：形成在半导体材料的集成结构的第一晶片（1）（3，4）包括半导体区域（10，12-15，20）和隔离区 （7，18）; 形成，具有能够与所述反应的金属材料制成，包括插头元件（32）的金属材料的半导体材料，互连结构（28-30，32）的至少一个接合区域（34）的第二晶片（25）上 所述第一晶片的半导体区域（10，12-15，20）（1）; （70 34）的插头元件（32）的与所述半导体区直接反应以形成金属硅化物并通过使接合区域的第一和第二晶片结合在一起。 由此，用于形成互连结构的冶金操作是用于处理硅所需的操作的完全呼叫独立的，因此thatthere没有干扰任何两组操作之间。 此外，其中两个晶片由这些区域可以是分开的，和互连结构可以用硅处理不相容的材料制成，没有污染的任何风险。

公开(公告)号：EP1162661A1

公开(公告)日：2001-12-12

申请号：EP00830407.3

申请日：2000-06-06

Applicant: STMicroelectronics S.r.l.

Inventor： Murari, Bruno ,  Mastromatteo, Ubaldo ,  Vigna, Benedetto

IPC: H01L23/58 ,  H01L23/36 ,  H01L23/31

CPC classification number: H01L24/01 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/4827 ,  H01L2224/274 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082

Abstract: The electronic device (15) is formed in a die including a body (2) of semiconductor material having a first face (9) covered by a covering structure (7, 10) and a second face (12). An integral spreader of metal is grown galvanically on the second face during the manufacture of a wafer, prior to cutting into dice. The covering structure (7, 10) comprises a passivation region (7) and a protective region (10) of opaque polyimide; the protective region (10) and the passivation region (7) are opened (11) above the contact pads (6) for the passage of leads (22).

Abstract translation: 电子器件（15）形成在包括半导体材料的主体（2）的模具中，该半导体材料的本体（2）具有由覆盖结构（7,10）和第二面（12）覆盖的第一面（9）。 在切割成骰子之前，在制造晶片期间，金属的整体式扩展器电镀在第二面上。 覆盖结构（7,10）包括钝化区域（7）和不透明聚酰亚胺的保护区域（10）; 保护区域（10）和钝化区域（7）在接触焊盘（6）上方打开（11）以引导引线（22）通过。

公开(公告)号：EP1151962A1

公开(公告)日：2001-11-07

申请号：EP00830314.1

申请日：2000-04-28

Applicant: STMicroelectronics S.r.l.

Inventor： Mastromatteo, Ubaldo ,  Ghironi, Fabrizio ,  Aina, Roberto ,  Bombonati, Mauro

IPC: B81C3/00 ,  H01L25/065 ,  H01L23/48 ,  G11B19/20

CPC classification number: B81C1/00238 ,  B81C2201/019 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01322

Abstract: The electric connection structure connects a first silicon body (10) to conductive regions (29, 30) provided on the surface of a second silicon body (1) arranged on the first body (10). The electric connection structure comprises at least one plug region (3) of silicon, which extends through the second body (1); at least one insulation region (2a, 6) laterally surrounding the plug region (3); and at least one conductive electromechanical connection region (23) arranged between the first body (10) and the second body (1), and in electrical contact with the plug region (3) and with conductive regions (15-19; 40) of the first body (10). To form the plug region (3), trenches (2a) are dug in a first wafer (1) and are filled, at least partially, with insulating material (6). Next, the plug region (3) is fixed to a metal region (23) provided on a second wafer (10), by performing a low-temperature heat treatment which causes a chemical reaction between the metal and the silicon. Subsequently, the first wafer (1) is thinned until the trenches (2a) and electrical connections (29, 30) are formed on the free face of the first wafer.

Abstract translation: 的电连接结构连接的第一硅体（10），以提供布置在第一主体（10）的第二硅本体（1）的表面上的导电区域（29，30）。 的电连接结构包括硅中的至少一个插塞区域（3），它通过所述第二主体延伸（1）; 至少一个绝缘区域（2A，6）横向围绕所述插头区域（3）; 和至少一个导电机电连接区域（23）与第一主体（10）和第二本体（1）之间以及在与所述插塞区域（3）的电接触，并与导电区域布置（15-19; 40）的 第一主体（10）。 为了形成插头区域（3），沟槽（2a）的挖在第一晶片（1）和被填充时，至少部分地与绝缘材料（6）。 接着，将插塞区域（3）被固定到设置在第二晶片（10）通过进行低温热处理这导致金属与硅之间的化学反应的金属区（23）。 随后，第一晶片（1）被减薄，直至沟槽（2a）和电连接（29，30）在所述第一晶片的自由面上形成。

公开(公告)号：EP1123739A1

公开(公告)日：2001-08-16

申请号：EP00830098.0

申请日：2000-02-11

Applicant: STMicroelectronics S.r.l.

Inventor： Mastromatteo, Ubaldo ,  Villa, Flavio ,  Barlocchi, Gabriele

IPC: B01L7/00 ,  B01L3/00 ,  B01J19/00

CPC classification number: B65D73/00 ,  A01G9/026 ,  B01J19/0093 ,  B01J2219/00873 ,  B01J2219/00961 ,  B01L3/5025 ,  B01L3/502707 ,  B01L3/502715 ,  B01L7/52 ,  B01L2200/12 ,  B01L2200/147 ,  B01L2300/0816 ,  B01L2300/1827 ,  B26D1/245 ,  B29C53/04 ,  B29C61/02 ,  B29L2009/00 ,  B32B3/28 ,  B32B7/02 ,  B32B37/144 ,  B32B38/1866 ,  B32B2307/736 ,  B44C3/04 ,  B44C3/044 ,  B44C3/087 ,  B44C5/005 ,  B44C5/06 ,  B44F1/14 ,  F28F2260/02 ,  Y10T156/1041 ,  Y10T156/1051 ,  Y10T156/1052 ,  Y10T428/2443

Abstract: The integrated device (1) for microfluid thermoregulation comprises a semiconductor material body (2) having a surface (3); a plurality of buried channels (4) extending in the semiconductor material body (2) at a distance from the surface (3) of the semiconductor material body (2); inlet and outlet ports (5a, 5b) extending from the surface (3) of the semiconductor material body (2) as far as the ends (4a, 4b) of the buried channels (4) and being in fluid connection with the buried channels; and heating elements (10) on the semiconductor material body. Temperature sensors (15) are arranged between the heating elements (10) above the surface (3) of the semiconductor material body (2).

Abstract translation: 微流体温度调节集成器件（1）包括（2）具有表面的半导体材料体（3）; 掩埋信道的在半导体材料体（2）以一定距离从表面延伸的多个（4）的半导体材料体（3）（2）; 入口和出口端口（5A，5B）从所述表面（3）延伸的半导体材料体（2），只要端部（4A，4B）掩埋信道（4）和与所述掩埋通道流体连接的 ; 和加热元件（10）在所述半导体材料体。 温度传感器（15）的半导体材料体（2）的表面（3）上方的加热元件（10）之间设置。