公开(公告)号：EP0913832B1

公开(公告)日：2003-07-23

申请号：EP97830566.2

申请日：1997-11-03

Applicant: STMicroelectronics S.r.l.

Inventor： Pasotti, Marco ,  Rolandi, Pier Luigi ,  Canegallo, Roberto ,  Gerna, Danilo ,  Chioffi, Ernestina

IPC: G11C11/56 ,  G11C27/00

CPC classification number: G11C11/5621 ,  G11C11/5628

公开(公告)号：EP0872850B1

公开(公告)日：2003-07-02

申请号：EP97830172.9

申请日：1997-04-14

Applicant: STMicroelectronics S.r.l.

Inventor： Gerna, Danilo ,  Canegallo, Roberto ,  Chioffi, Ernestina ,  Pasotti, Marco ,  Rolandi, Pier Luigi

IPC: G11C27/00 ,  G11C16/06

CPC classification number: G11C16/28 ,  G11C27/005

公开(公告)号：EP1220228A1

公开(公告)日：2002-07-03

申请号：EP00830866.0

申请日：2000-12-29

Applicant: STMicroelectronics S.r.l.

Inventor： Pasotti, Marco ,  De Sandre, Guido ,  Guaitini, Giovanni ,  Iezzi, David ,  Poles, Marco ,  Rolandi, PierLuigi

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/28 ,  G11C16/04

CPC classification number: G11C16/34 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/28

Abstract: Described herein is a method for storing a datum in a first and a second memory cells of a nonvolatile memory. The storage method envisages programming the first and second memory cells in a differential way, by setting a first threshold voltage in the first memory cell and a second threshold voltage different from the first threshold voltage in the second memory cell, the difference between the threshold voltages of the two memory cells representing a datum stored in the memory cells themselves.

Abstract translation: 这里描述了一种用于将数据存储在非易失性存储器的第一和第二存储单元中的方法。 存储方法设想通过在第一存储单元中设置第一阈值电压和与第二存储单元中的第一阈值电压不同的第二阈值电压来以差分方式对第一和第二存储单元进行编程，阈值电压 表示存储在存储单元本身中的数据的两个存储器单元。

公开(公告)号：EP1139210A1

公开(公告)日：2001-10-04

申请号：EP00830228.3

申请日：2000-03-28

Applicant: STMicroelectronics S.r.l.

Inventor： Rocchi, Alessandro ,  Bisio, Marco ,  Pasotti, Marco ,  Rolandi, Pier Luigi

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7211

Abstract: An architecture of a FLASH memory organized in a plurality of physical sectors wherein read, write and erase operations of data occupying a fractional memory space of any one of said physical sectors are carried out, may include splitting a physical sector in a plurality of singularly addressable logic sectors. Each logic sector (j) is defined by a memory space of pre-established size (PAYLOAD j ), a chain pointer (CHAIN_PTR j ) assuming a neutral value (NULL) or a value pointing directly or indirectly to a second logic sector associated to a respective chain pointer (CHAIN_PTR 2 ) at neutral value (NULL), a status indicator (STATUS j ) assuming a first value (FREE) if the logic sector is empty, a second value (OD) if the data contained in it belongs to the logic sector, a third value (NOD) if the data do not belong to the logic sector, or a fourth value (DEL) if the data has been erased, and a remap pointer (REMAP_PTR j ) assuming the neutral value (NULL) or a value pointing directly or indirectly to the chain pointer (CHAIN_PTR 3 ) of a third logic sector.
A further improvement consists in attributing to each physical sector a logical address (LOGICAL_ADDRESS) permitting to destine to the function of temporary buffer, for partly erasing the content of a physical sector, in rotation all the physical sectors, not to repeatedly stressing the same sector.

Abstract translation: 组织在多个物理扇区中的FLASH存储器的架构，其中执行占用任何一个所述物理扇区的分数存储器空间的数据的读，写和擦除操作，包括分割多个可单独寻址的物理扇区 逻辑部门。 每个逻辑扇区（j）由预先确定的大小（PAYLOADj）的存储器空间，假定中性值（NULL）的链指针（CHAIN_PTRj）或直接或间接指向与相应的第二逻辑扇区 链路指针（CHAIN_PTR2）为中性值（NULL），如果逻辑扇区为空则假定为第一值（FREE）的状态指示符（STATUSj），如果其中包含的数据属于逻辑扇区，则为第二值（OD） 如果数据不属于逻辑扇区，则为第三值（NOD），如果数据已经被擦除则为第四值（DEL），以及假设中性值（NULL）或直接指向的值的重映射指针（REMAP_PTRj） 或间接地连接到第三逻辑扇区的链指针（CHAIN_PTR3）。 进一步的改进在于将归属于每个物理扇区的逻辑地址（LOGICAL_ADDRESS）允许指定临时缓冲区的功能，以部分地擦除物理扇区的内容，旋转所有物理扇区，而不是反复强调同一扇区 。

公开(公告)号：EP0766257B1

公开(公告)日：2001-04-11

申请号：EP95830397.6

申请日：1995-09-27

Applicant: STMicroelectronics S.r.l.

Inventor： Gerna, Danilo ,  Pasotti, Marco ,  Marchese, Stefano

IPC: G11C27/00 ,  G11C27/02

CPC classification number: G11C27/00 ,  G11C27/024

公开(公告)号：EP0987715A1

公开(公告)日：2000-03-22

申请号：EP98830536.3

申请日：1998-09-15

Applicant: STMicroelectronics S.r.l.

Inventor： Pasotti, Marco ,  Lhermet, Frank ,  Rolandi, Pier Luigi

IPC: G11C11/56 ,  G11C16/06

CPC classification number: G11C16/3431 ,  G11C11/5621 ,  G11C16/3418

Abstract: The method includes restoring the charge lost from memory cells, such as to restore the original voltage levels, within a time equivalent to the retention time. The decision concerning when the memory is to be restored is taken for example when the memory is switched on, based on the time elapsed since the previous programming/restoration, or based on the difference between the present threshold voltage of the reference cells and the original threshold voltage of the (suitably stored) reference cells, or when predetermined operating conditions occur. This makes it possible to prolong the life of nonvolatile memories, in particular of multilevel type, wherein the retention time decreases as the number of levels (bits/cell) is increased.

Abstract translation: 该方法包括在等同于保留时间的时间内恢复从存储器单元丢失的电荷，例如恢复原始电压电平。 基于从上一次编程/恢复之后经过的时间，或者基于参考单元的当前阈值电压与原始值之间的差异，例如当存储器被接通时，采用关于何时恢复存储器的决定 （适当存储的）参考单元的阈值电压，或者当发生预定操作条件时。 这使得可以延长非易失性存储器的使用寿命，特别是延长多级电路的寿命，其中保持时间随着电平数（位/电池）的增加而减少。

公开(公告)号：EP0877386A1

公开(公告)日：1998-11-11

申请号：EP97830216.4

申请日：1997-05-09

Applicant: STMicroelectronics S.r.l.

Inventor： Rolandi, Pierluigi ,  Canegallo, Roberto ,  Chioffi, Ernestina ,  Gerna, Danilo ,  Pasotti, Marco

IPC: G11C27/00

CPC classification number: G11C27/005

Abstract: For each cell (1) to be programmed, the present threshold value (V o ) of the cell is determined; the desired threshold value (V TAR ) is acquired; the analog distance between the present threshold value and the desired threshold value is calculated; and a programming pulse (S) is then generated, the duration of which is proportional to the analog distance calculated. The programming and reading cycle is repeated until the desired threshold is reached. By this means a time saving is obtained, owing to the reduction of the number of intermediate reading steps. The method permits programming in parallel and simultaneously of a plurality of cells (1) of a memory array (2) which is connected to a single word line (5 1 ) and to different bit lines (4 1 - 4 N ), each with a programming pulse (S 1 - S N ) the duration of which is proportional to the analog distance calculated for the same cell. The programming process is thus very fast, owing to parallel application of the programming and the saving in the intermediate reading cycles.

Abstract translation: 对于每个电池（1）要被编程，本阈值（VO）的单元的是确定性的矿洞; 所需的阈值（VTAR）被获取; 本阈值和阈值之间的模拟距离要的计算出; 并然后产生一编程脉冲（S），所有的持续时间成比例的计算值模拟距离。 重复编程和读取周期，直到达到所需的阈值。 通过这种方式一个省时的获得，由于中间步骤读取的数目的减少。 该方法允许在并行和同时单元的多个编程（1），其连接到一个单一的字线（51）和到不同的位线（41 - 4N）的存储器阵列（2）所有的，每一个编程脉冲 （S1 - SN）的所有的持续时间成比例的用于相同小区中计算出的模拟距离。 编程过程因此是非常快的，由于编程的并行应用和中间读周期节省。

公开(公告)号：EP0872850A1

公开(公告)日：1998-10-21

申请号：EP97830172.9

申请日：1997-04-14

Applicant: STMicroelectronics S.r.l.

Inventor： Gerna, Danilo ,  Canegallo, Roberto ,  Chioffi, Ernestina ,  Pasotti, Marco ,  Rolandi, Pier Luigi

IPC: G11C27/00 ,  G11C16/06

CPC classification number: G11C16/28 ,  G11C27/005

Abstract: An analog reading circuit (10) comprising a current mirror circuit (19) forcing two identical currents into a cell (2) to be read and into a reference cell (27) and an operational amplifier (31) having an inverting input connected to the drain terminal (13) of the cell (2) to be read, a non-inverting input connected to the drain terminal (28) of the reference cell (27) and an output connected to the gate terminal (30) of the reference cell. The reference cell (27) therefore forms part of a negative feedback loop which maintains the overdrive voltages of the cell (2) to be read and the reference cell (27) constant, irrespective of temperature variations. The reading circuit (10) is also of high precision and has a high reading speed.

Abstract translation: 一种模拟读取电路（10），包括电流镜电路（19），将两个相同的电流强制进入待读取的单元（2）并进入参考单元（27）;以及运算放大器（31），其具有与 要读取的单元（2）的漏极端子（13），连接到参考单元（27）的漏极端子（28）的非反相输入端和连接到参考单元（20）的栅极端子（30）的输出端 。 因此，参考单元（27）形成负反馈回路的一部分，其保持要读取的单元（2）的过驱动电压和参考单元（27）恒定，而与温度变化无关。 读取电路（10）也具有高精度且读取速度高的特点。