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    Array of vertical bipolar junction transistors, in particular selectors in a phase change memory device
    31.
    发明公开
    Array of vertical bipolar junction transistors, in particular selectors in a phase change memory device 审中-公开
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    公开(公告)号：EP1965427A1

    公开(公告)日：2008-09-03

    申请号：EP07425107.5

    申请日：2007-02-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Magistretti, Michele ,  Pellizzer, Fabio ,  Benvenuti, Augusto

    IPC: H01L27/102

    CPC classification number: H01L27/1022 ,  H01L21/76205 ,  H01L21/76224 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: A process for manufacturing an array of bipolar transistors, wherein deep field insulation regions (26) of dielectric material are formed in a semiconductor body (21), thereby defining a plurality of active areas (22), insulated from each other and a plurality of bipolar transistors are formed in each active area. In particular, in each active area, a first conduction region (24) is formed at a distance from the surface of the semiconductor body (21); a control region (25) is formed on the first conduction region (24); and, in each control region, at least two second conduction regions (31) and at least one control contact region (36) are formed. The control contact region (36) is interposed between the second conduction regions (31) and at least two surface field insulation regions (29) are thermally grown in each active area (22) between the control contact region (36) and the second conduction regions (31).

    Abstract translation: 一种用于制造双极晶体管阵列的方法，其中介电材料的深场绝缘区域（26）形成在半导体本体（21）中，从而限定出彼此绝缘的多个有源区域（22）和多个 在每个有效区域中形成双极晶体管。 特别地，在每个有源区域中，形成与半导体本体（21）的表面相距一定距离的第一导电区域（24）。 在所述第一导电区域（24）上形成控制区域（25）。 并且在每个控制区域中形成至少两个第二导电区域（31）和至少一个控制接触区域（36）。 控制接触区域（36）介于第二导电区域（31）之间，并且至少两个表面场绝缘区域（29）在控制接触区域（36）和第二导电区域（36）之间的每个有源区域（22）中热生长 地区（31）。

    Phase change memory cell with tubular heater and manufacturing method thereof
    33.
    发明公开
    Phase change memory cell with tubular heater and manufacturing method thereof 有权
    Phasenwechselspeicher mitrohrförmigerHeizstruktur sowie deren Herstellungsverfahren

    公开(公告)号：EP1710807A1

    公开(公告)日：2006-10-11

    申请号：EP05102811.6

    申请日：2005-04-08

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pellizzer, Fabio ,  Varesi, Enrico ,  Pirovano, Agostino

    IPC: G11C16/02 ,  H01L45/00

    CPC classification number: H01L45/06 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

    Abstract: A phase change memory cell includes a phase change region of a phase change material, a heating element (30) of a resistive material, arranged in contact with the phase change region (33') and a memory element (35) formed in said phase change region at a contact area with the heating element (30). The contact area is in the form of a frame that has a width of sublithographic extent (S) and, preferably, a sublithographic maximum external dimension. The heating element (30) includes a hollow elongated portion which is arranged in contact with the phase change region (33').

    Abstract translation: 相变存储单元包括相变材料的相变区域，与相变区域（33'）接触地布置的电阻材料的加热元件（30）和形成在所述相位中的存储元件（35） 在与加热元件（30）的接触区域处的变化区域。 接触区域为具有亚光刻范围（S）的宽度的框架的形式，并且优选为亚光刻最大外部尺寸。 加热元件（30）包括与相变区域（33'）接触地布置的中空细长部分。

    Writing circuit for a phase change memory device
    34.
    发明公开
    Writing circuit for a phase change memory device 有权
    SchreibschaltungfürPhasenwechsel-Speicher

    公开(公告)号：EP1489622A1

    公开(公告)日：2004-12-22

    申请号：EP03425390.6

    申请日：2003-06-16

    Applicant: STMicroelectronics S.r.l.

    Inventor： Resta, Claudio ,  Bedeschi, Ferdinando ,  Pellizzer, Fabio ,  Casagrande, Giulio

    IPC: G11C11/34

    CPC classification number: G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

    Abstract: A memory device (20) of a phase change type, wherein a memory cell (2) has a memory element (3) of calcogenic material switcheable between at least two phases associated with two different states of the memory cell. A write stage (24) is connected to the memory cell and has a capacitive circuit (35) configured to generate a discharge current used as write current having no constant portion and causing the memory cell (2) to change state.

    Abstract translation: 一种相变型存储器件（20），其中存储单元（2）具有可在存储单元的两种不同状态相关联的至少两相之间切换的钙质材料的存储元件（3）。 写入级（24）连接到存储单元，并具有电容电路（35），其被配置为产生用作不具有常数部分的写入电流的放电电流，并使存储器单元（2）改变状态。

    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array manufactured thereby
    39.
    发明公开
    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array manufactured thereby 有权
    一种用于制备在铜镶嵌技术相变存储器阵列以及将相变存储器相应产生阵列处理

    公开(公告)号：EP1505656A1

    公开(公告)日：2005-02-09

    申请号：EP03425536.4

    申请日：2003-08-05

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pellizzer, Fabio ,  Bez, Roberto

    IPC: H01L27/24

    CPC classification number: H01L27/2472 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    Abstract: A process for manufacturing a phase change memory array, includes the steps of: forming a plurality of PCM cells (33), arranged in rows and columns; and forming a plurality of resistive bit lines (35) for connecting PCM cells (33) arranged on a same column, each resistive bit lines (35) comprising a respective phase change material portion (31'), covered by a respective barrier portion (32'). After forming the resistive bit lines (35), electrical connection structures (45, 52) for the resistive bit lines (35) are formed directly in contact with the barrier portions (32') of the resistive bit lines (35).

    Abstract translation: 一种用于制造相变存储器阵列的方法，包括以下步骤：形成PCM单元的多个（33），以行和列布置; 以及形成电阻的位线用于连接PCM单元布置在同一列有多个（35）（33），每个电阻的位线（35），其包括respectivement相变材料部分（31“）中，由一个respectivement阻挡部分覆盖（ 32“）。 形成用于电阻的位线电阻的位线（35），电连接结构（45，52）之后，（35）直接与所述电阻的位线（35）的阻挡部分（32“）接触而形成。

    Architecture of a phase-change nonvolatile memory array
    40.
    发明公开
    Architecture of a phase-change nonvolatile memory array 有权
    建筑工人工程师协会

    公开(公告)号：EP1326254A1

    公开(公告)日：2003-07-09

    申请号：EP01830806.4

    申请日：2001-12-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Khouri, Osama ,  Bedeschi, Ferdinando ,  Bosisio, Giorgio ,  Pellizzer, Fabio

    IPC: G11C11/34

    CPC classification number: G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: The phase-change nonvolatile memory array (8) is formed by a plurality of memory cells (10, 10') extending in a first and in a second direction orthogonal to each other. A plurality of column-selection lines (11) extend parallel to the first direction. A plurality of word-selection lines (12) extend parallel to the second direction. Each memory cell (10, 10') includes a PCM storage element (15) and a selection transistor (16). A first terminal of the selection transistor is connected to a first terminal of the PCM storage element, and the control terminal of the selection transistor is connected to a respective word-selection line (12). A second terminal of the PCM storage element (15) is connected to a respective column-selection line (11), and a second terminal of the selection transistor (16) is connected to a reference-potential region (18) while reading and programming the memory cells (10, 10').

    Abstract translation: 相变非易失性存储器阵列（8）由在彼此正交的第一和第二方向上延伸的多个存储单元（10,10'）形成。 多个列选择线（11）平行于第一方向延伸。 多个字选择线（12）平行于第二方向延伸。 每个存储单元（10,10'）包括PCM存储元件（15）和选择晶体管（16）。 选择晶体管的第一端子连接到PCM存储元件的第一端子，并且选择晶体管的控制端子连接到相应的字选择线（12）。 PCM存储元件（15）的第二端子连接到相应的列选择线（11），并且选择晶体管（16）的第二端子连接到参考电位区域（18），同时读取和编程 存储单元（10,10'）。

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