公开(公告)号：EP2506411B1

公开(公告)日：2014-12-17

申请号：EP12162766.5

申请日：2012-03-30

Applicant: STMicroelectronics S.r.l.

Inventor： Ucciardello, Carmelo ,  Conte, Antonino ,  Pagano, Santi

IPC: H02M3/07

CPC classification number: H02M3/073 ,  H02M2003/076 ,  Y10T29/49117

公开(公告)号：EP1876600B1

公开(公告)日：2009-09-09

申请号：EP06425465.9

申请日：2006-07-06

Applicant: STMicroelectronics S.r.l.

Inventor： Castaldo, Enrico ,  Conte, Antonino ,  Lo Giudice, Gianbattista

IPC: G11C5/14 ,  H02M3/07

CPC classification number: G11C5/145 ,  G11C16/12

公开(公告)号：EP1566723B1

公开(公告)日：2007-11-21

申请号：EP04100682.6

申请日：2004-02-20

Applicant: STMicroelectronics S.r.l.

Inventor： Castaldo, Enrico ,  Conte, Antonino ,  Torrisi, Salvatore ,  Sambataro, Vincenzo

IPC: G06F1/26 ,  G11C16/30

CPC classification number: G06F1/26 ,  G11C16/30

公开(公告)号：EP1814121A1

公开(公告)日：2007-08-01

申请号：EP06425047.5

申请日：2006-01-31

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Annunziata, Roberto ,  Zuliani, Paola

IPC: G11C16/04 ,  G11C16/08

CPC classification number: G11C16/0433

Abstract: A memory architecture (10) is described of the type comprising at least one matrix (2) of memory cells of the EEPROM type (3) organised in rows or word lines (WL) and columns or bit lines (BL), each memory cell (3) comprising a floating gate cell transistor (MC) and a selection transistor (TS) and being connected to a source line (SL) shared by the matrix (2). The memory cells (3) are organised in words (6), all the memory cells (3) belonging to a same word (6) being driven by a byte switch (5), in turn connected to at least one control gate line (CGT).
Advantageously according to the invention, the memory cells (3) have accessible substrate terminals connected to a first additional line (EEW).
Also a biasing method of a memory architecture is described.

Abstract translation: 描述了包括以行或字线（WL）和列或位线（BL）组织的EEPROM类型（3）的存储器单元的至少一个矩阵（2）的类型的存储器架构（10），每个存储器单元 （3），包括浮置栅极单元晶体管（MC）和选择晶体管（TS），并连接到由矩阵（2）共享的源极线（SL）。 存储单元（3）以单词（6）组织，属于由字节开关（5）驱动的相同单词（6）的所有存储单元（3）依次连接到至少一个控制栅极线 CGT）。 有利地，根据本发明，存储器单元（3）具有连接到第一附加线（EEW）的可访问衬底端子。 还描述了存储器架构的偏置方法。

公开(公告)号：EP1727153A1

公开(公告)日：2006-11-29

申请号：EP05104465.9

申请日：2005-05-25

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Sberno, Giampiero ,  Micciche', Mario ,  Castaldo, Enrico

IPC: G11C16/16

CPC classification number: G11C16/16

Abstract: A non-volatile memory device is proposed. The memory device (100) includes a plurality of blocks (115) of memory cells (125), each block having a common biasing node (SL) for all the memory cells of the block, biasing means (150) for providing a biasing voltage, and selection means (140, 145) for selectively applying the biasing voltage to the biasing node of a selected block, for each block the selection means including first switching means (N8, N9, N10) and second switching means (N7) connected in series, the first switching means being connected with the biasing node and the second switching means being connected with the biasing means, wherein the second switching means of all the blocks are connected in parallel, the selection means including means (145) for closing the first switching means of the selected block and the second switching means of all the blocks, and for opening the second switching means of each unselected block.

Abstract translation: 提出了一种非易失性存储器件。 存储器件（100）包括存储器单元（125）的多个块（115），每个块具有用于块的所有存储单元的公共偏置节点（SL），偏置装置（150）用于提供偏置电压 以及用于选择性地将偏置电压施加到所选块的偏置节点的选择装置（140,145），对于每个块，选择装置包括第一开关装置（N8，N9，N10）和第二开关装置（N7） 所述第一开关装置与所述偏置节点连接，所述第二开关装置与所述偏置装置连接，其中所述块的所述第二开关装置并联连接，所述选择装置包括用于闭合所述第一开关装置的装置， 所有块的切换装置和所有块的第二切换装置，并且用于打开每个未选择块的第二切换装置。

公开(公告)号：EP0936621B1

公开(公告)日：2006-04-26

申请号：EP98830067.9

申请日：1998-02-13

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Demange, Nicolas

IPC: G11C7/06 ,  G11C16/06

CPC classification number: G11C7/067 ,  G11C16/26

公开(公告)号：EP1566723A1

公开(公告)日：2005-08-24

申请号：EP04100682.6

申请日：2004-02-20

Applicant: STMicroelectronics S.r.l.

Inventor： Castaldo, Enrico ,  Conte, Antonino ,  Torrisi, Salvatore ,  Sambataro, Vincenzo

IPC: G06F1/26 ,  G11C16/30

CPC classification number: G06F1/26 ,  G11C16/30

Abstract: A power management unit (115) for a non-volatile memory device (100) is proposed. The power management unit includes means (125) for providing a reference voltage, resistive means (Rr) for deriving a reference current from the reference voltage, means (135 1 -135 n ) for generating a plurality of operative voltages from a power supply voltage, and means (145 1 -145 n ) for regulating the operative voltages; in the power management unit of the invention, for each operative voltage the means for regulating includes means (220) for deriving a scaled reference current from the reference current according to a scaling factor, further resistive means (245 i ) for deriving a rating voltage from the scaled reference current, means (220,245 i ) for deriving a measuring voltage from the operative voltage and the rating voltage, and means (250 i ) for controlling the operative voltage according to a comparison between the measuring voltage and the reference voltage.

Abstract translation: 一种功率管理单元（115），用于非易失性存储器装置（100）被提议。 功率管理单元包括用于从参考电压导出的参考电流的装置（1351-135n），用于从电源电压产生工作电压的多元化提供参考电压，电阻装置（RR）手段（125），和 装置（1451-145n），用于调节所述工作电压; 在本发明的功率管理单元，对于每个操作电压的装置，用于调节包括​​用于从所述基准电流雅丁缩放参考电流的缩放因子，另外电阻装置（245I），用于从导出的评价电压的装置（220） 缩放的参考电流的装置（220,245i），用于从所述操作电压和额定电压的测量电压的装置，以及（250I），用于控制工作电压gemäß到测量电压和所述基准电压之间的比较。

公开(公告)号：EP0936621A1

公开(公告)日：1999-08-18

申请号：EP98830067.9

申请日：1998-02-13

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Demange, Nicolas

IPC: G11C7/06 ,  G11C16/06

CPC classification number: G11C7/067 ,  G11C16/26

Abstract: Memory sense amplifier, specifically EEPROM memories, operating in an extended supply voltage range, comprising a comparator that on an input receives a signal available on a bit line representative of the current flowing through the read memory cell and on another input it receives a signal representative of a reference current available on another bit line, and a bit lines polarization system.
According to this invention the comparator comprises a stage in common source configuration (N2) and an active load (P5) for said stage.
Moreover, the bit lines polarization system releases a polarization value (VBL) independent from the supply voltage value (VDD).

Abstract translation: 存储器读出放大器，特别是EEPROM存储器，在扩展电源电压范围内操作的方法，包括一个比较器做了在输入端接收表示所述电流的位线流过读取存储单元并在另一个输入提供的信号接收到的信号代表 另一个位线提供参考电流，和一个位线的偏振系统。。根据本发明中的比较器包括在共用源极配置（N 2）和到有源负载（P5）用于所述阶段的阶段。 更上方，位线偏振系统释放独立于电源电压值（VDD）的偏振值（VBL）。