公开(公告)号：KR101287097B1

公开(公告)日：2013-07-16

申请号：KR1020120005252

申请日：2012-01-17

Applicant: 서강대학교산학협력단

Inventor： 이승훈 ,  박혜림 ,  남상필 ,  송정은

IPC: H03M1/38

CPC classification number: H03M1/1205 ,  H03M1/0607 ,  H03M1/38 ,  H03M2201/2233 ,  H03M2201/615

Abstract: PURPOSE: A four channel pipe line SAR ADC minimized mismatching between channels is provided to remove amplifier offset mismatching between channels and to minimize electricity consumption and an area. CONSTITUTION: Four channel pipe line SAR ADC comprises a first SAR ADC (100), a remaining voltage amplifier (110), a second SAR ADC (120) and a digital correction circuit (130). For pieces of 6 bit SAR ADC in the first step is composed of SAR ADC with four channels connected in parallel. The remaining voltage amplifier is connected to an output unit of the first SAR ADC and is shared in four channels with a couple of input units. The second SAR ADC is composed of SAR ADC in four channels connected in parallel which tests remaining voltage which is amplified in the remaining voltage amplifier. The digital correction circuit corrects errors of digital output which comes out of the first SAR ADC and the second SAR ADC.

Abstract translation: 目的：四通道管线SAR ADC最小化通道之间的失配，以消除通道之间的放大器偏移不匹配，并最大限度地减少用电量和面积。 构成：四通道管线SAR ADC包括第一SAR ADC（100），剩余电压放大器（110），第二SAR ADC（120）和数字校正电路（130）。 对于6位SAR ADC，第一步由具有四个通道并联的SAR ADC组成。 剩余的电压放大器连接到第一SAR ADC的输出单元，并在四个通道中共享几个输入单元。 第二个SAR ADC由四路并联的SAR ADC组成，测试剩余电压放大器中剩余的电压。 数字校正电路校正了从第一SAR ADC和第二SAR ADC引出的数字输出的误差。

公开(公告)号：KR1020130013826A

公开(公告)日：2013-02-06

申请号：KR1020110075672

申请日：2011-07-29

Applicant: 김도율

Inventor： 조해성

IPC: H03M1/12

CPC classification number: H03M1/0607 ,  H03M1/12 ,  H03M2201/615 ,  H03M2201/622

Abstract: PURPOSE: A gain control system for generating high quality digital data is provided to obtain a large gain corresponding to an environment, thereby heightening the quality of generated digital data. CONSTITUTION: An analog signal input unit(1100) receives an analog signal. A gain processing unit(1200) controls gain of an analog-digital converter(ADC). The ADC(1300) converts analog signal handled with gain into a digital signal. A digital data output unit(1400) outputs a converted digital signal. The gain processing unit includes a step(A) of setting gain as a predetermined level of the first gain; a step(B) of sensing peak generation during an analog-digital conversion process; and step(C) of determining a necessity of gain decreasing regulation by inspecting peak generation in step(B). The gain processing unit includes a step (D) of lowering the gain to the second gain level lower than the first gain level, decreasing by a predetermined gain decrease unit. [Reference numerals] (1000) ADC system; (1100) Analog signal input unit; (1200) Gain processing unit; (1210) Gain monitoring unit; (1220) Gain control policy unit; (1221) Peak occurrence time policy unit; (1222) Peak occurrence recovery policy unit; (1230) Gain control unit; (1300) Analog-digital converter; (1400) Digital data output unit

Abstract translation: 目的：提供用于产生高质量数字数据的增益控制系统，以获得与环境相对应的大增益，从而提高生成的数字数据的质量。 构成：模拟信号输入单元（1100）接收模拟信号。 增益处理单元（1200）控制模数转换器（ADC）的增益。 ADC（1300）将用增益处理的模拟信号转换为数字信号。 数字数据输出单元（1400）输出转换的数字信号。 增益处理单元包括将增益设置为第一增益的预定电平的步骤（A）; 在模拟数字转换处理期间感测峰值产生的步骤（B）; 以及步骤（C），其通过检查步骤（B）中的峰值生成来确定增益减小调节的必要性。 增益处理单元包括将增益降低到低于第一增益水平的第二增益水平的步骤（D），减小预定增益减小单元。 （参考数字）（1000）ADC系统; （1100）模拟信号输入单元; （1200）增益处理单元; （1210）增益监控单元; （1220）收益控制政策单位; （1221）峰值发生时间策略单位; （1222）高峰发生恢复政策单位; （1230）增益控制单元; （1300）模拟数字转换器; （1400）数字数据输出单元

公开(公告)号：KR1020090114706A

公开(公告)日：2009-11-04

申请号：KR1020080040484

申请日：2008-04-30

Applicant: 삼성전자주식회사

Inventor： 김성우 ,  김영식

IPC: H03M1/66 ,  H03M3/02

CPC classification number: H03M3/458 ,  H03M1/0621 ,  H03M1/12 ,  H03M3/02 ,  H03M2201/615 ,  H03M2201/63

Abstract: PURPOSE: A delta-sigma analog digital converter is provided to minimize a noise level in a passband by controlling a zero point of a signal transfer function and noise transfer function independently. CONSTITUTION: In a delta-sigma analog digital converter, an adder(110) unites an input signal and a feedback signal. A forward loop filter(120) converts an output signal of the adder. The forward loop filter filters the signal outputted from the adder. A quantizer(130) quantizes the signal outputted from the forward loop filter, and the feedback loop filter(140) converts the signal outputted from the quantizer. The feedback loop filter outputs a changed signal. A controller controls the forward loop filter and determines a zero point of a transfer function of the forward loop filter according to interference signal information.

Abstract translation: 目的：提供Δ-Σ模拟数字转换器，通过独立地控制信号传递函数和噪声传递函数的零点来最小化通带中的噪声电平。 构成：在Δ-Σ模拟数字转换器中，加法器（110）将输入信号和反馈信号相结合。 正向环路滤波器（120）转换加法器的输出信号。 正交环滤波器对从加法器输出的信号进行滤波。 量化器（130）量化从正向环路滤波器输出的信号，并且反馈环路滤波器（140）转换从量化器输出的信号。 反馈环路滤波器输出改变的信号。 控制器控制正向环路滤波器，并根据干扰信号信息确定正向环路滤波器的传递函数的零点。

公开(公告)号：KR1020090085283A

公开(公告)日：2009-08-07

申请号：KR1020080011092

申请日：2008-02-04

Applicant: 주식회사 포스코아이씨티

Inventor： 양병훈 ,  김광섭

IPC: H03M1/12

CPC classification number: H03M1/1023 ,  H03M1/0607 ,  H03M1/12 ,  H03M2201/615 ,  H03M2201/6381

Abstract: An apparatus and a method for compensating an error of an analog to digital converter are provided to compensate a gain error and an offset error of the analog to digital converter by calculating the gain error and the offset error from a first digital output about the first reference voltage and a second digital output about the second reference voltage. A reference voltage generator(110) generates a first reference voltage and a second reference voltage for compensating an error of an analog to digital converter. An analog to digital converter(120) converts the analog input signal into the digital output. The analog to digital converter receives the first and second reference voltages and generates the first digital output and the second digital output. A calculator(140) calculates the gain and offset errors of the analog to digital converter by detecting the first and second digital outputs. An error compensating unit(130) compensates for the error of the digital output generated in the analog to digital converter based on the calculated gain and offset error.

Abstract translation: 提供了用于补偿模数转换器的误差的装置和方法，用于通过从关于第一参考的第一数字输出计算增益误差和偏移误差来补偿模数转换器的增益误差和偏移误差 电压和关于第二参考电压的第二数字输出。 参考电压发生器（110）产生用于补偿模数转换器的误差的第一参考电压和第二参考电压。 模数转换器（120）将模拟输入信号转换成数字输出。 模数转换器接收第一和第二参考电压并产生第一数字输出和第二数字输出。 计算器（140）通过检测第一和第二数字输出来计算模数转换器的增益和偏移误差。 误差补偿单元（130）基于所计算的增益和偏移误差补偿在模数转换器中产生的数字输出的误差。

公开(公告)号：KR1020080010580A

公开(公告)日：2008-01-31

申请号：KR1020060070774

申请日：2006-07-27

Applicant: 연세대학교 산학협력단

Inventor： 강성호 ,  김기철 ,  김인철

IPC: H03M1/10

CPC classification number: H03M1/1071 ,  H03M1/1038 ,  H03M1/12 ,  H03M2201/615 ,  H03M2201/63 ,  H03M2201/657

Abstract: A histogram based ADC(Analog-Digital Converter) BIST(Built-In Self-Test) for hardware overhead optimization is provided to perform a test with an operation speed by applying the BIST to an ADC test. A histogram based ADC(Analog-Digital Converter) BIST(Built-In Self-Test) for hardware overhead optimization includes a signal generator(20), a comparator(40), and a result analyzer(30). The signal generator generates a test signal applied to the input of an ADC(10). The comparator outputs a test end signal when the signal generated from the signal generator reaches maximum voltage. The result analyzer outputs an offset, a gain, and an NL(Differential/Integral non-linearity) value by analyzing the output of the ADC. The result analyzer has a transition detector to detect the generation of transition through the LSB(Least Significant Bit) of the output of the ADC, and a counter device to count transition signals outputted from the transition detector.

Abstract translation: 提供用于硬件开销优化的基于直方图的ADC（模数转换器）BIST（内置自检），通过将BIST应用于ADC测试来执行具有操作速度的测试。 用于硬件开销优化的基于直方图的ADC（模拟数字转换器）BIST（内置自检）包括信号发生器（20），比较器（40）和结果分析器（30）。 信号发生器产生施加到ADC（10）的输入端的测试信号。 当信号发生器产生的信号达到最大电压时，比较器输出一个测试结束信号。 结果分析仪通过分析ADC的输出输出偏移，增益和NL（微分/积分非线性）值。 结果分析仪具有一个转换检测器，用于检测通过ADC输出的LSB（最低有效位）产生的转换，以及用于计数从转换检测器输出的转换信号的计数器件。

公开(公告)号：KR1020060005837A

公开(公告)日：2006-01-18

申请号：KR1020040054817

申请日：2004-07-14

Applicant: 삼성전자주식회사

Inventor： 변상욱

IPC: H03M1/10 ,  H03M1/70

CPC classification number: H03M1/0607 ,  H03M1/0621 ,  H03M1/70 ,  H03M1/742 ,  H03M2201/615 ,  H03M2201/6327 ,  H03M2201/639

Abstract: 출력 범위를 가변할 수 있고, 미세하게 출력전압을 가변할 수 있는 디지털/아날로그 변환기 및 디지털/아날로그 변환방법이 개시되어 있다. 디지털/아날로그 변환기는 커런트 셀, 기준전류소스, 및 출력저항을 포함한다. 기준전류소스는 가변적인 기준전류를 흘려주고, 커런트 셀이 공급할 수 있는 최대전류가 기준전류의 2배가 되도록 한다. 디지털/아날로그 변환방법은 전류제공단계, 기준전류제공단계, 및 출력전압제공단계를 포함한다. 기준전류제공단계는 가변적인 기준전류를 흘려주고, 전류제공단계에서 제공하는 최대전류의 크기가 기준전류의 2배가 되도록 한다. 따라서, 디지털/아날로그 변환기의 출력범위를 가변할 수 있고, 미세하게 출력전압을 가변할 수 있다.

Abstract translation: 公开了能够改变输出范围并且精细地改变输出电压的数字/模拟转换器和数字/模拟转换方法。 数字 - 模拟转换器包括电流单元，参考电流源和输出电阻器。 参考电流源流过可变的参考电流，使得可由当前单元提供的最大电流是参考电流的两倍。 数字/模拟转换方法包括电流提供步骤，参考电流提供步骤和输出电压提供步骤。 参考电流提供步骤允许可变的参考电流流动，并且在电流提供步骤中提供的最大电流的大小是参考电流的两倍。 因此，数模转换器的输出范围可以改变，并且输出电压可以精细地改变。

公开(公告)号：KR1020030015933A

公开(公告)日：2003-02-26

申请号：KR1020010049784

申请日：2001-08-18

Applicant: 엘지전자 주식회사

Inventor： 정현숙

IPC: H03M1/12

CPC classification number: H03M1/0607 ,  H03M2201/615

Abstract: PURPOSE: A digital DC offset compensation device is provided, which compensates an offset detected from an average value of output samples of an A/D converter to an output signal of the A/D converter. CONSTITUTION: An A/D(Analog/Digital) converter(20) digitalizes an analog input signal. And a digital compensation unit(30) detects a digital DC offset signal by subtracting an ideal average value of an analog signal from an average value of the A/D converter output samples, and compensate a digital signal by subtracting the digital DC offset from the digital output signal of the A/D converter. An automatic gain control unit(50) calculates a gain control value corresponding to the output signal of the A/D converter. And an amplification unit(10) amplifies an input signal to be inputted to the A/D converter with the above gain control value.

Abstract translation: 目的：提供一个数字直流偏移补偿装置，用于补偿从A / D转换器的输出样本的平均值检测到的偏移量与A / D转换器的输出信号。 构成：A / D（模拟/数字）转换器（20）对模拟输入信号进行数字化。 并且数字补偿单元（30）通过从A / D转换器输出样本的平均值中减去模拟信号的理想平均值来检测数字DC偏移信号，并且通过从数/模转换器输出样本的平均值中减去数字DC偏移来补偿数字信号 A / D转换器的数字输出信号。 自动增益控制单元（50）计算与A / D转换器的输出信号对应的增益控制值。 并且放大单元（10）利用上述增益控制值放大要输入到A / D转换器的输入信号。