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公开(公告)号：KR1020020056354A
公开(公告)日：2002-07-10
申请号：KR1020000085684
申请日：2000-12-29
Applicant: 권오경
Inventor： 권오경
IPC: H03M1/76
CPC classification number: H03M1/68 , H03M2201/62
Abstract: PURPOSE: A method for transforming digital to analog and apparatus thereof is provided to reduce manufacturing costs by embodying a digital to analog transformer with a small surface. CONSTITUTION: A digital to analog transformer comprises three sample and hold circuits(101-103), a pair of capacitors(C1,C2), a first, a second and a third switches(SW1-SW3), and a controller(110) controlling entire operations. The digital to analog transformer additionally includes a pair of reference voltages(VH,VL) supplied from the outer, and mode control signals(Vsh1-Vsh3) controlling the sample and hold circuits(101-103) by the controller(110). At this time, the sample and hold circuits(101- 103) are used for keeping voltages generated by voltage distributions of the reference voltages(VH,VL) and the capacitors(C1,C2).
Abstract translation: 目的：提供一种用于转换数字到模拟的方法及其装置，以通过体现具有小表面的数模转换器来降低制造成本。 构成：数模转换器包括三个采样和保持电路（101-103），一对电容器（C1，C2），第一，第二和第三开关（SW1-SW3）和控制器（110） 控制整个操作。 数模转换器还包括从外部提供的一对参考电压（VH，VL）和由控制器（110）控制采样和保持电路（101-103）的模式控制信号（Vsh1-Vsh3）。 此时，采样保持电路（101-103）用于保持由参考电压（VH，VL）和电容器（C1，C2）的电压分布产生的电压。
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公开(公告)号：KR1020020046485A
公开(公告)日：2002-06-21
申请号：KR1020000076681
申请日：2000-12-14
Applicant: 매그나칩 반도체 유한회사
Inventor： 문홍식
IPC: H03M1/76
CPC classification number: H03M1/76 , H03M2201/62 , H03M2201/6372
Abstract: PURPOSE: A D/A(Digital to Analog) transformer is provided to reduce a linear error due to discordance between resistors and an occupied area by decreasing the number of resistors necessary for generating an analog level in half. CONSTITUTION: A D/A transformer comprises a reference current source(Iref) for deciding a voltage level of resistors(R) arrayed in series, a reference voltage source(Vcom) for supplying a center voltage of an output signal of the D/A transformer, switches(SW1-SW6) for varying a voltage level by changing a flow direction of a current flowing to the arrayed resistors(R), a decoder(10) for selecting an output level by decoding a digital signal, and a buffer(20) for supplying an analog signal by buffering the analog signal selected from the decoder(10).
Abstract translation: 目的：提供D / A（数字到模拟）变压器，通过减少将模拟电平降低一半所需的电阻数量，减少由于电阻和占用区域之间的不一致引起的线性误差。 构成：AD / A变压器包括用于决定串联排列的电阻器（R）的电压电平的参考电流源（Iref），用于提供D / A变压器的输出信号的中心电压的参考电压源（Vcom） 用于通过改变流向阵列电阻器（R）的电流的流动方向来改变电压电平的开关（SW1-SW6），用于通过解码数字信号来选择输出电平的解码器（10）和缓冲器 ），用于通过缓冲从解码器（10）中选择的模拟信号来提供模拟信号。
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公开(公告)号：KR101834975B1
公开(公告)日：2018-04-20
申请号：KR1020170029311
申请日：2017-03-08
Applicant: 충북대학교 산학협력단
CPC classification number: H03M1/38 , H03M1/1245 , H03M2201/62 , H03M2201/8152
Abstract: 본발명은분리형단조연속근사아날로그디지털변환기에관한것으로서, 연속근사레지스터(SAR) 제어로직에의해스위칭제어에대응하여입력신호인제1입력신호(V)와제2입력신호(V)를입력받아샘플동작및 홀드동작을수행하는샘플홀드부와, 샘플홀드시간동안제1입력신호와제2입력신호에대해각각에대응되는출력전압값인제1출력신호와제2출력신호로생성하며, 브릿지커패시터(C)를상위비트또는하위비트를결정하기위한커패시터어레이를 2단구조로형성한커패시터어레이와, 샘플홀드부와연동되어상위비트또는하위비트를결정하는스위치(S7)와, 제1출력신호와제2출력신호의크기를비교하여비교결과에따라디지털값을출력하는비교기와, 디지털값에대응하여최종디지털코드값을결과신호로출력하는연속근사레지스터제어로직을포함한다. 본발명에따르면, 분리형과단조를조합하여커패시터개수감소, 에너지효율향상, 커패시터크기구현가능, 정확도향상등의효과를기대할수 있다.
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公开(公告)号：KR1020140119894A
公开(公告)日：2014-10-13
申请号：KR1020130033840
申请日：2013-03-28
Applicant: 한국과학기술원
IPC: H03M1/12
CPC classification number: H03M1/504 , H03M1/1245 , H03M2201/2366 , H03M2201/62
Abstract: The present invention relates to an ADC which stores information in a time axis and processes the same with low power. To provide an ADC which realizes low power though a composition which does not increase complexity according to resolution, the ADC stores information in a time axis and processes the same, and has a composition for realizing a binary search algorithm. Also, to solve the above-stated objective, an analog-digital converter according to one aspect of the present invention is provided.
Abstract translation: 本发明涉及一种在时间轴上存储信息并以低功率进行处理的ADC。 为了提供通过不根据分辨率增加复杂度的组合实现低功率的ADC，ADC将时间轴上的信息存储在处理器中，并且具有用于实现二进制搜索算法的组合。 此外，为了解决上述目的，提供了根据本发明的一个方面的模拟数字转换器。
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公开(公告)号：KR1020140046129A
公开(公告)日：2014-04-18
申请号：KR1020120112167
申请日：2012-10-10
Applicant: (주)제퍼로직
Inventor： 박희종
CPC classification number: H03M1/66 , G02F1/133 , G09G3/36 , H03M2201/62 , H03M2201/932
Abstract: Disclosed are a digital-analog converter, a device for driving a liquid crystal display device including the digital-analog converter, and a liquid crystal display device. The digital-analog converter generates a grayscale voltage corresponding to a digital signal applied from the outside from a plurality of reference grayscale voltages and outputs the grayscale voltage. To this end, the digital-analog converter includes an intermediate grayscale voltage selection unit for selecting two intermediate grayscale voltages from among the reference grayscale voltages and a grayscale voltage generation unit for generating the grayscale voltage from the intermediate grayscale voltages, wherein the grayscale voltage generation unit generates the grayscale voltage according to preset k bits among m bits of the digital signals. Furthermore, the intermediate grayscale voltage selection unit includes a first selection unit for selecting a first intermediate grayscale voltage using a decoder of m-k bits excluding k bits from m bits and a second selection unit including a plurality of decoders from a 1-bit decoder to an (m-k-1) bit decoder to select a second intermediate grayscale voltage different from the first intermediate grayscale voltage. As described above, the second selection unit of the intermediate grayscale voltage selection unit is formed of not a single decoder corresponding to the number of provided bits but a plurality of decoders having smaller number of bits, and thus, the number of required transistors can be remarkably reduced. [Reference numerals] (AA) 1-bit decoder; (BB) 2-bit decoder; (CC) 3-bit decoder; (DD) 4-bit decoder
Abstract translation: 公开了一种数模转换器，用于驱动包括数模转换器的液晶显示装置的装置和液晶显示装置。 数模转换器从多个参考灰度电压产生对应于从外部施加的数字信号的灰度电压并输出灰度电压。 为此，数模转换器包括用于从参考灰度电压中选择两个中间灰度电压的中间灰度电压选择单元和用于从中间灰度电压产生灰度电压的灰度级电压产生单元，其中灰阶电压产生 单位根据数字信号的m位中的预设k位产生灰度电压。 此外，中间灰度级电压选择单元包括：第一选择单元，用于使用从m位除去k位的mk位的解码器以及包括从1位解码器到多位解码器的多个解码器的第二选择单元来选择第一中间灰度电压 （mk-1）位解码器，以选择不同于第一中间灰度电压的第二中间灰度电压。 如上所述，中间灰度级电压选择单元的第二选择单元不是与提供的位数相对应的单个解码器，而是具有较少位数的多个解码器，因此所需晶体管的数量可以是 明显减少 （附图标记）（AA）1位解码器; （BB）2位解码器; （CC）3位解码器; （DD）4位解码器
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Patent Agency Ranking
公开(公告)号：KR1020120015155A
公开(公告)日：2012-02-21
申请号：KR1020100077436
申请日：2010-08-11
Applicant: 정태경
IPC: H03M1/12
CPC classification number: H03M1/361 , H03M1/002 , H03M1/1205 , H03M2201/2216 , H03M2201/2291 , H03M2201/62
Abstract: PURPOSE: A structure and method of circuit design for implementing low power consumption and a minimum area for a flash analog to digital converter are provided to simplify the structure of a convertor for low power consumption by reducing the number of repeated elements. CONSTITUTION: An analog to digital converter(100) includes a FDBD(First maximum bit determination) unit(110) and a SCTH(Signal Conversion to Half Signal) unit(120) The converter comprises a buffer(111), a resistance ladder(130), an amplification and comparison unit(140), an encoder(150), and XNOR(Exclusive NOR) logic unit(160). The FDBD unit outputs a corresponding signal by determining a MSB(Most Significant Bit) value. The SCTHO unit generates an absolute value signal(Vsmall) about the difference between an input analog signal and a 1/2 of a voltage. A whole circuit size and power consumption shrink by reducing the complex elements of the resistance ladder, the amplification and comparison unit, and the encoder.
Abstract translation: 目的：提供用于实现低功耗和闪存模数转换器的最小面积的电路设计的结构和方法，以通过减少重复元件的数量来简化用于低功耗的转换器的结构。 构成：模数转换器（100）包括FDBD（第一最大位确定）单元（110）和SCTH（信号转换为半信号）单元（120）。转换器包括缓冲器（111），电阻梯（ 130），放大和比较单元（140），编码器（150）和XNOR（异或逻辑）逻辑单元（160）。 FDBD单元通过确定MSB（最高有效位）值来输出相应的信号。 SCTHO单元产生关于输入模拟信号和电压的1/2之间的差的绝对值信号（Vsmall）。 通过减少电阻梯，放大和比较单元以及编码器的复杂元件，可以缩小整个电路尺寸和功耗。
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公开(公告)号：KR1020110108563A
公开(公告)日：2011-10-06
申请号：KR1020100027825
申请日：2010-03-29
Applicant: 서강대학교산학협력단
IPC: H03M1/12
CPC classification number: H03M1/121 , H03M1/002 , H03M1/14 , H03M1/361 , H03M2201/62 , H03M2201/932
Abstract: 본 발명은 가변 이득 증폭기를 갖는 ADC에 관한 것으로서, 복수의 FLASH ADC들과 복수의 MDAC들을 포함하는 N(N은 자연수) 단으로 구성된 파이프라인 구조의 ADC에 있어서, 첫 번째 단의 제 1 FLASH ADC와 첫 번째 단의 제 1 MDAC에 입력신호가 입력되기 전에, GCB에 의해 제어되고, 이득 조절 기능을 갖는 VGA를 포함하는 것을 특징으로 하고, VGA는 복수의 단위 샘플링 커패시터들을 포함하고, ADC의 입력신호를 샘플링하는 커패시터와 GCB에 의해 선택된 적어도 하나 이상의 단위 샘플링 커패시터를 이용하여 이득을 조절하는 것을 특징으로 하며, 다양한 시스템에 응용이 가능하도록 이득 조절 기능을 갖고, AFE 응용시 전력 소모 및 면적을 최소화할 수 있다.
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38.发明公开
公开(公告)号：KR1020110106568A
公开(公告)日：2011-09-29
申请号：KR1020100025672
申请日：2010-03-23
Applicant: 고려대학교 산학협력단
IPC: H03M1/66
CPC classification number: H03M1/14 , H03M1/002 , H03M1/48 , H03M2201/62 , H03M2201/8152 , H03M2201/932
Abstract: 본 발명은 캐패시터의 직렬연결을 이용하여 멀티플라잉 디지털 아날로그 변환기의 구성에 사용되는 캐패시터의 숫자를 줄여 칩 면적과 소모 전력을 줄인 멀티플라잉 디지털 아날로그 변환기 및 이를 이용한 파이프라인 아날로그 디지털 변환기에 관한 것으로, 본 발명에 따른 멀티플라잉 디지털 아날로그 변환기는 샘플링페이즈에서 입력전압을 입력받고 증폭페이즈에서 상기 샘플링페이즈에서 보다 캐패시턴스 값이 줄어드는 제1캐패시터부; 상기 샘플링페이즈에서 상기 입력전압을 입력받고 상기 증폭페이즈에서 디지털 전압을 입력받는 제2캐패시터부; 및 상기 샘플링페이즈에서 상기 제1캐패시터부와 상기 제2캐패시터부가 입력받은 입력전압과 상기 증폭페이즈에서 상기 제2캐패시터부가 입력받은 디지털전압의 차이를 증폭한 레지듀 전압을 출력하기 위한 증폭부를 포함하고, 상기 제1캐패시터부는 상기 증폭페이즈에서 상기 증폭부의 입력노드와 출력노드사이에 네거티브 피드백 루프를 이루는 것을 특징으로 한다.
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公开(公告)号：KR1020110090669A
公开(公告)日：2011-08-10
申请号：KR1020100010598
申请日：2010-02-04
Applicant: 건국대학교 산학협력단 , 광운대학교 산학협력단
CPC classification number: H03M1/46 , H03M1/002 , H03M1/361 , H03M2201/2216 , H03M2201/2233 , H03M2201/62
Abstract: PURPOSE: An ADC(Analog to Digital Converter) with a successive approximation register is provided to reduce a design area by simply changing the structure of an analog to digital converter with a SAR(Successive Approximation Register). CONSTITUTION: A reference unit(100) generates the reference voltage of a conversion section. A timing unit(500) generates the reference time for the total conversion process of an analog input signal. A digital error correction unit(600) mixes conversion codes in a digital part based on the reference generated in the timing unit. The digital error correction unit generates the digital total conversion codes of the analog input signal. The conversion codes in a digital part are generated in a first flash ADC(ANALOG TO DIGITAL CONVERTER,200) and a second flash ADC(300).
Abstract translation: 目的：提供具有逐次逼近寄存器的ADC（模数转换器），通过简单地通过SAR（连续逼近寄存器）改变模数转换器的结构来减少设计区域。 构成：参考单元（100）产生转换部分的参考电压。 定时单元（500）产生模拟输入信号的总转换处理的基准时间。 数字纠错单元（600）基于在定时单元中生成的参考来混合数字部分中的转换代码。 数字纠错单元产生模拟输入信号的数字总转换代码。 数字部分中的转换代码在第一闪存ADC（模拟到数字转换器，200）和第二闪存ADC（300）中生成。
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公开(公告)号：KR1020110049504A
公开(公告)日：2011-05-12
申请号：KR1020090106547
申请日：2009-11-05
Applicant: 주식회사 티엘아이
IPC: H03M1/66
CPC classification number: H03M1/66 , H03M2201/16 , H03M2201/62 , H03M2201/932
Abstract: PURPOSE: A digital to analog converter is provided to converts a plurality of digital signals to each analog signal by using a fine resistance string and to share fine resistance string. CONSTITUTION: A conversion unit includes a switching unit(GSC), and a resistive unit(GMF), and a fine switching unit(GSF). The switching unit generates a plurality of fist high voltage and first a low voltage. The fine switching unit is connected between a first high voltage and a first low voltage. The fine switching unit includes resistances which generates a plurality of first fine voltages. The fine switching unit generates the first analog signal and the second analog signal.
Abstract translation: 目的：提供数模转换器，通过使用细电阻串将多个数字信号转换成每个模拟信号并共享细电阻串。 构成：转换单元包括切换单元（GSC）和电阻单元（GMF）以及精细切换单元（GSF）。 开关单元产生多个第一高电压和第一低电压。 精细开关单元连接在第一高电压和第一低电压之间。 精细切换单元包括产生多个第一精细电压的电阻。 精细切换单元产生第一模拟信号和第二模拟信号。
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