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公开(公告)号：EP1962567A2
公开(公告)日：2008-08-27
申请号：EP08250012.5
申请日：2008-01-03
Applicant: Hitachi, Ltd.
Inventor： Sueyoshi, Junya
CPC classification number: H05K3/308 , H01R12/585 , H05K3/325 , H05K2201/092 , H05K2201/10189 , H05K2201/10303 , H05K2201/1059 , H05K2201/10878
Abstract: Provided is a printed wiring board (2) formed with a through-hole (21) into which a press-fit pin (1) is press-fitted. The printed wiring board includes at least one signal transmission layer, a signal transmission wiring pattern (22a) formed in the signal transmission layer, and an electrode portion of the signal transmission wiring pattern exposed at an inner circumferential surface (21 b) of the through-hole. The electrode portion is not formed covering the entire inner circumferential surface of the through-hole but at a part of the inner circumferential surface of the through-hole.
Abstract translation: 提供一种形成有压配合销（1）的通孔（21）的印刷线路板（2）。 印刷布线板包括至少一个信号传输层，形成在信号传输层中的信号传输布线图案（22a）和暴露在通孔的内周表面（21b）处的信号传输布线图案的电极部分 -孔。 电极部未形成为覆盖通孔的整个内周面，但在通孔的内周面的一部分。
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公开(公告)号：EP0713359A1
公开(公告)日：1996-05-22
申请号：EP95116868.1
申请日：1995-10-26
Applicant: International Business Machines Corporation
Inventor： Bhatt, Anilkumar Chinuprasad , Magnuson, Roy Harvey , Markovich, Voya Rista , Papathomas, Konstantinos , Powell, Douglas Oliver
CPC classification number: H05K3/0094 , H01L23/5384 , H01L2224/16 , H01L2224/16225 , H01L2924/01004 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H05K1/112 , H05K3/0023 , H05K3/429 , H05K3/4602 , H05K2201/092 , H05K2201/09472 , H05K2201/09509 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/09845 , H05K2201/10734 , H05K2203/0191 , H05K2203/0278 , Y10T29/49126 , Y10T29/49165
Abstract: Disclosed is a printed circuit board and a method of preparing the printed circuit board. The printed circuit board (1) has two types of plated through holes. The first type of plated through holes (7a) extend to and through an exterior surface of the printed circuit board for receipt of a pin-in-through-hole module or component pin. The second type of plated through holes (7b) are for surface mount technology and terminate below the exterior surface of the printed circuit board. These plated through holes contain a fill composition (11).
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33.发明公开
公开(公告)号：EP0483979A1
公开(公告)日：1992-05-06
申请号：EP91309053.6
申请日：1991-10-02
Applicant: NOKIA MOBILE PHONES LTD.
Inventor： Pienimaa, Seppo
CPC classification number: H05K3/426 , H05K1/115 , H05K3/0023 , H05K3/184 , H05K3/429 , H05K3/4602 , H05K2201/092 , H05K2201/09845
Abstract: The invention relates to a method for producing printed circuit boards. According to the method the base material of the PCB is subjected to the following subsequent processing stages:
a) holes (3) are made by punching,
b) the copper cladding is cleaned by mechanical and/or chemical techniques,
c) using image transfer and etching, a pattern (4) is produced,
d) a photoimageable polymer insulating layer (5) is applied to the surfaces of the PCB,
e) the PCB is subjected to exposure and development,
f) the PCB is subjected to an adhesion improvement and activation treatment necessary for chemical deposition of metal,
g) image transfer is performed using a photoimageable and developable insulating layer (7),
h) chemical deposition of metallization (8) is applied in which process the desired conductor patterns, contact areas and interconnections are produced onto the activated areas not protected with the photoimageable insulating layer,
i) a solder mask (9) is applied to PCB that protects the conductor pattern at other areas except those intended for establishing contacts.Abstract translation: 本发明涉及印刷电路板的制造方法。 根据该方法，PCB的基材经受以下后续处理阶段：a）通过冲压制成孔（3），b）通过机械和/或化学技术清洁铜包层，c）使用图像转印 和蚀刻，产生图案（4），d）将可光成像的聚合物绝缘层（5）施加到PCB的表面，e）PCB经受曝光和显影，f）PCB经受粘附 金属化学沉积所需的改进和激活处理，g）使用可光成像和可显影的绝缘层（7）进行图像转印，h）应用化学沉积金属化（8），其中所需的导体图案，接触面积和 在未被光致成像绝缘层保护的激活区域上产生互连，i）将焊接掩模（9）施加到PCB，以保护除旨在建立的那些之外的其它区域处的导体图案 联系人
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34.发明公开Photosensitive resin composition for forming conductor patterns and multilayer circuit boards using same 失效用于形成导体图案的感光性树脂组合物和使用其的多层电路板
公开(公告)号：EP0428870A3
公开(公告)日：1992-03-11
申请号：EP90119995.0
申请日：1990-10-18
Applicant: HITACHI, LTD.
Inventor： Imabayashi, Shinichiro , Oka, Hitoshi , Tanaka, Isamu , Kikuchi, Hiroshi , Watanabe, Makio
CPC classification number: H05K3/185 , G03F7/004 , G03F7/028 , H05K3/0023 , H05K3/426 , H05K3/429 , H05K3/4602 , H05K3/4661 , H05K2201/0145 , H05K2201/092 , H05K2201/09845
Abstract: A resin composition for forming conductor patterns comprising a photo curable resin, a photopolymerization initiator, a thermosetting resin, photosensitive semiconductor particles, and if necessary a polyfunctional unsaturated compound is suitable for forming very fine conductor patterns in a build-up method.
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公开(公告)号：NL2005656C
公开(公告)日：2012-05-10
申请号：NL2005656
申请日：2010-11-09
Applicant: ELECTROMAGNETIC COMPATIBILITY MCC B V
Inventor： COENEN MARTINUS JACOBUS
IPC: H05K1/02
CPC classification number: H05K1/0231 , H05K1/0234 , H05K1/0246 , H05K2201/092 , H05K2201/09309 , H05K2201/10446
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Patent Agency Ranking36.发明授权MICROELECTRONIC SUBSTRATES WITH THERMALLY CONDUCTIVE PATHWAYS AND METHODS OF MAKING SAME 有权随着对导热插入和方法MICRO电子基板及其
公开(公告)号：EP1639870B8
公开(公告)日：2011-01-12
申请号：EP04751551.5
申请日：2004-05-07
Applicant: Viasystems Corporation
Inventor： JOHNSON, Benny, H.
CPC classification number: H05K1/0204 , H05K3/4046 , H05K3/4611 , H05K2201/092 , H05K2201/09845 , H05K2201/10416
Abstract: This disclosure suggests microelectronic substrates with thermally conductive pathways. In one implementation, such a substrate includes a body and a thermally conductive member. The Body has a first surface that includes a microelectronic component mounting site, a second surface separated from the first surface by a thickness, and an opening extending through at least a portion of the thickness. The opening is outwardly open at one or both of the surfaces and has a first portion having a first transverse dimension and a second portion having a larger second transverse dimension. The thermally conductive member includes a first thickness, which is received in the first portion of the opening , and a second thickness , which is received in the second portion of the opening. A transverse dimension of the second thickness of the thermally conductive member is greater than the first transverse dimension of the opening.
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37.发明授权MICROELECTRONIC SUBSTRATES WITH THERMALLY CONDUCTIVE PATHWAYS AND METHODS OF MAKING SAME 有权随着对导热插入和方法MICRO电子基板及其
公开(公告)号：EP1639870B1
公开(公告)日：2010-11-17
申请号：EP04751551.5
申请日：2004-05-07
Applicant: Merix Corporation
Inventor： JOHNSON, Benny, H.
CPC classification number: H05K1/0204 , H05K3/4046 , H05K3/4611 , H05K2201/092 , H05K2201/09845 , H05K2201/10416
Abstract: This disclosure suggests microelectronic substrates with thermally conductive pathways. In one implementation, such a substrate includes a body and a thermally conductive member. The Body has a first surface that includes a microelectronic component mounting site, a second surface separated from the first surface by a thickness, and an opening extending through at least a portion of the thickness. The opening is outwardly open at one or both of the surfaces and has a first portion having a first transverse dimension and a second portion having a larger second transverse dimension. The thermally conductive member includes a first thickness, which is received in the first portion of the opening , and a second thickness , which is received in the second portion of the opening. A transverse dimension of the second thickness of the thermally conductive member is greater than the first transverse dimension of the opening.
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公开(公告)号：EP0483979B1
公开(公告)日：1995-12-27
申请号：EP91309053.6
申请日：1991-10-02
Applicant: NOKIA MOBILE PHONES LTD.
Inventor： Pienimaa, Seppo
CPC classification number: H05K3/426 , H05K1/115 , H05K3/0023 , H05K3/184 , H05K3/429 , H05K3/4602 , H05K2201/092 , H05K2201/09845
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39.发明公开Verfahren zur Herstellung einer zwei- oder mehrlagigen Verdrahtung und danach hergestellte zwei- oder mehrlagige Verdrahtung 失效一种用于产生二维或多层布线过程，并且此后产生二维或多层布线。
公开(公告)号：EP0645953A1
公开(公告)日：1995-03-29
申请号：EP94114453.7
申请日：1994-09-14
Applicant: Siemens NV , BULCKE HYBRID TECHNOLOGY BVBA , INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW
Inventor： van Puymbroeck, Josef , Bulcke, Fred , Beyne, Eric, Dr.
CPC classification number: H05K1/183 , H01L21/4803 , H01L23/13 , H01L23/49855 , H01L24/48 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/12042 , H01L2924/15153 , H01L2924/15157 , H01L2924/15165 , H01L2924/181 , H01L2924/3025 , H05K3/027 , H05K3/062 , H05K3/284 , H05K3/4602 , H05K3/4697 , H05K2201/09118 , H05K2201/092 , H05K2203/1581 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
Abstract: Auf einem durch Spritzgießen hergestellten und mit einer Mulde (M) versehenen Substrat (S) werden nacheinander eine erste Leiterebene (LE1), eine Dielektrikumsschicht (DS) und eine zweite Leiterebene (LE2) erzeugt, worauf in die Mulde (M) ein elektronisches Bauelement (B) eingebracht wird, die Anschlüsse (A) des Bauelements (B) mit zugeordneten Anschlußflächen (AF) auf dem Substrat (S) vorzugsweise durch Bonden elektrisch leitend verbunden werden und dann durch Füllen der Mulde (M) mit Kunststoff eine Verkapselung (V) für das Bauelement (B) gebildet wird. Es entsteht ein kompakter, dünner Aufbau mit einer hohen Verdrahtungsdichte. Durch die versunkene Montage und Verkapselung von Bauelementen in Mulden des spritzgegossenen Substrats wird neben der Dickenreduzierung ein optimaler Schutz von Bauelement und dessen Anschlußverdrahtung erzielt.
Abstract translation: 第一导体平面（LE1），介电层（DS）和第二导体面（LE2）是在一个基片（S）连续地产生的所有其通过注射成型制造，并且设置有一个槽（M），afterwhich到 电子部件（B）插入到槽（M），组分（B）的连接（A）导电地连接到在基片（S）相关联的连接面（AF），优选通过键合，和封装（ V）的组分（B）然后，通过填充所述槽（M）用塑料制成。 其结果是一个紧凑的，薄型设计，具有高布线密度。 成分的波谷在组件的注塑成型的基板结果凹入安装和封装及其连接布线是OPTI马利保护，除了厚度减小。
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公开(公告)号：KR1020100026400A
公开(公告)日：2010-03-10
申请号：KR1020080085389
申请日：2008-08-29
Applicant: 에스케이하이닉스 주식회사
Inventor： 서민석
IPC: H01L23/48
CPC classification number: H01L23/481 , H01L23/49811 , H01L23/49827 , H01L24/13 , H01L24/29 , H01L24/32 , H01L25/0657 , H01L2224/0554 , H01L2224/05573 , H01L2224/05647 , H01L2224/13021 , H01L2224/13025 , H01L2225/06541 , H01L2225/06551 , H01L2225/06572 , H01L2924/00014 , H01L2924/01078 , H01L2924/078 , H01L2924/15311 , H01L2924/19042 , H01L2924/19043 , H05K1/183 , H05K1/184 , H05K2201/092 , H05K2201/10674 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
Abstract: PURPOSE: A substrate for a semiconductor package and the semiconductor package area provided to improve the operational property of semiconductor chips by equalizing the lengths of signal path which is applied to a plurality of the semiconductor chips. CONSTITUTION: A substrate body(110) includes a first side(111) and a second side(112) which opposes to the fist side. A through electrode(120) passes through the first side and the second side. Insulation units(130) of a block shape is arranged on the first side. A connection unit(140) includes a first conductive part(142) and a second conductive part(144) which are electrically connected to the through electrode. The second conductive part is electrically connected to the first conductive part and is exposed to the both side of the insulation units.
Abstract translation: 目的：一种用于半导体封装的衬底和半导体封装区域，用于通过均衡施加到多个半导体芯片的信号路径的长度来提高半导体芯片的操作性能。 构成：衬底主体（110）包括与第一侧相对的第一侧（111）和第二侧（112）。 贯通电极（120）穿过第一侧和第二侧。 在第一侧设置块状的绝缘单元（130）。 连接单元（140）包括电连接到通孔的第一导电部分（142）和第二导电部分（144）。 第二导电部分电连接到第一导电部分并暴露于绝缘单元的两侧。
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