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    SLANTED GLASS EDGE FOR IMAGE SENSOR PACKAGE
    392.
    发明公开
    SLANTED GLASS EDGE FOR IMAGE SENSOR PACKAGE 审中-公开

    公开(公告)号：EP3923334A1

    公开(公告)日：2021-12-15

    申请号：EP21177013.6

    申请日：2021-06-01

    Applicant: STMicroelectronics Pte Ltd.

    Inventor： HERARD, Laurent ,  GANI, David

    IPC: H01L27/146

    Abstract: Disclosed herein is a digital image sensor package including an image sensor substrate and a glass covering. The image sensor substrate carries photodiodes. The glass covering has a bottom surface, a top surface opposite the bottom surface, and a sidewall delimiting a perimeter edge of the glass covering. The glass covering overlies the photodiodes. A surface area of the top surface of the glass covering is greater than a surface area of the bottom surface of the glass covering such that the sidewall is anti-perpendicular to the top and bottom surfaces of the glass.

    POWER MOSFET WITH REDUCED CURRENT LEAKAGE AND METHOD OF FABRICATING THE POWER MOSFET
    393.
    发明公开
    POWER MOSFET WITH REDUCED CURRENT LEAKAGE AND METHOD OF FABRICATING THE POWER MOSFET 审中-公开

    公开(公告)号：EP3916800A1

    公开(公告)日：2021-12-01

    申请号：EP21174461.0

    申请日：2021-05-18

    Applicant: STMicroelectronics Pte Ltd.

    Inventor： YONG, Yean Ching

    IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78

    Abstract: An integrated circuit includes a polysilicon region that is doped with a dopant. A portion of the polysilicon region is converted to a polyoxide region which includes un-oxidized dopant ions. A stack of layers overlies over the polyoxide region. The stack of layers includes: a first ozone-assisted sub-atmospheric pressure thermal chemical vapor deposition (O 3 SACVD) TEOS layer; and a second O 3 SACVD TEOS layer; wherein the first and second O 3 SACVD TEOS layers are separated from each other by a dielectric region. A thermally annealing is performed at a temperature which induces outgassing of passivation atoms from the first and second O 3 SACVD TEOS layers to migrate to passivate interface charges due to the presence of un-oxidized dopant ions in the polyoxide region.

    WAFER LEVEL CHIP SCALE PACKAGE WITH CO-PLANAR BUMPS WITH DIFFERENT SOLDER HEIGHTS AND CORRESPONDING MANUFACTURING METHOD
    394.
    发明公开
    WAFER LEVEL CHIP SCALE PACKAGE WITH CO-PLANAR BUMPS WITH DIFFERENT SOLDER HEIGHTS AND CORRESPONDING MANUFACTURING METHOD 审中-公开

    公开(公告)号：EP3852139A2

    公开(公告)日：2021-07-21

    申请号：EP20215558.6

    申请日：2020-12-18

    Applicant: STMicroelectronics Pte Ltd.

    Inventor： GANI, David

    IPC: H01L23/485 ,  H01L21/60

    Abstract: The present disclosure is directed to a wafer level chip scale package (WLCSP) (100, 200, 300) with bumps with various combinations of conductive structures such as solder (118, 120, 214, 216, 314, 316) and under bump metallizations (UBMs) (112, 117, 311, 312) having different structures and different amounts of solder (118, 120, 214, 216, 314, 316) coupled to the UBMs (112, 117, 311, 312). Although the bumps have different structures and the volume (height) of solder (118, 120, 214, 216, 314, 316) differs, the total standoff height along the WLCSP (100, 200, 300) remains substantially the same. Each portion of solder (118, 120, 214, 216, 314, 316) includes a point furthest away from an active surface (103, 203, 303) of a die (102, 202, 302) of the WLCSP (100, 200, 300). Each point of each respective portion of solder (118, 120, 214, 216, 314, 316) is co-planar with each other respective point of the other respective portions of solder (118, 120, 214, 216, 314, 316). Additionally, the bumps with different structures are positioned accordingly on the active surface of the die (102, 202, 302) of the WLCSP (100, 200, 300) to reduce failures that may result from the WLCSP (100, 200, 300) being exposed to thermal cycling or the WLCSP (100, 200, 300) being dropped, or because of electromigration, in that less solder (118, 120, 214, 216, 314, 316) is used for bumps at corners of the WLCSP (100, 200, 300). The bumps with less solder comprise an additional contact structure (116, 212, 310) on which the solder (120, 214, 314) is formed. The bumps may be placed on a conductive redistribution layer (108, 208) or on contact pads (304) on the active surface (303) of the die (302) without a redistribution layer. During the manufacturing process, the conductive material (428) of the conductive structures (the solder) is filled in openings (424, 426) of a stencil (422), followed by removing excess portions of the conductive material (428) on the stencil (422) by a squeegee (430).

    AREA EFFICIENT REALIZATION OF COEFFICIENT ARCHITECTURE FOR BIT-SERIAL FIR, IIR FILTERS AND COMBINATIONAL/SEQUENTIAL LOGIC STRUCTURE WITH ZERO LATENCY CLOCK OUTPUT
    398.
    发明公开
    AREA EFFICIENT REALIZATION OF COEFFICIENT ARCHITECTURE FOR BIT-SERIAL FIR, IIR FILTERS AND COMBINATIONAL/SEQUENTIAL LOGIC STRUCTURE WITH ZERO LATENCY CLOCK OUTPUT 有权
    FOR BIT SERIAL FIR，IIR滤波器和组合/顺序逻辑结构无延迟系数建筑面积高效生产

    公开(公告)号：EP1119909A1

    公开(公告)日：2001-08-01

    申请号：EP98950601.9

    申请日：1998-10-13

    Applicant: STMicroelectronics Pte Ltd. ,  STMicroelectronics Limited

    Inventor： MALIK, Rakesh,STMicroelectronics Limited ,  GOEL, Puneet

    IPC: H03H17/02

    CPC classification number: H03H17/0225

    Abstract: The invention relates to area efficient realization of coefficient block [A] or architecture [A] with hardware sharing techniques and optimizations applied to this block. The block [A] is connected to coefficient lines CLin_0, CLin_1...CLin_n and BLin_0, BLin_1,... BLin_n coming from block [E] and/or [F], to be connected to perform filtering operation or a mathematical computing operation with optimization in hardware and provides a zero latency output. The invention also gives the area minimal realization of digital filters based on coefficient block [A], when operated in bit serial fashion. The optimization techniques and structure of the present invention are good for linear digital filters typically a finite impulse response (FIR) filter, infinite impulse response filter (IIR) and for other filters and applications based on combinational logic consisting of delay element (T), multiplier (M), adder (SA) and subtractor (SS).

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