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公开(公告)号：US10882296B2
公开(公告)日：2021-01-05
申请号：US16199565
申请日：2018-11-26
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Shang-Chi Wang , Yun-Han Yeh , Cyuan-Bang Wu
Abstract: A film-peeling apparatus is adapted to peel a protective film on a surface of a substrate. The surface of the substrate has a bare area which is not covered by the protective film. The film-peeling apparatus includes a punching member, a connector connected to the punching member, and a controller. The controller is configured for driving, through the connector, the punching member to punch at predetermined positions nearby or on a first edge of the protective film adjacent to the bare area.
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公开(公告)号：US10405423B2
公开(公告)日：2019-09-03
申请号：US15863605
申请日：2018-01-05
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Chiao-Cheng Chang , Yi-Nong Lin
Abstract: A multi-layer circuit board includes a first circuit board, conducting blocks, a second circuit board, and conducting recesses. The first circuit board has a first conductor layer mounted on the first circuit board. The conducting blocks are mounted on the first circuit board and electrically connected to the first conductor layer. The second circuit board has a second conductor layer mounted thereon and facing the first circuit board. The conducting recesses are formed in the second circuit board, electrically connected to the second conductor layer, and corresponding to the respective conducting blocks. The insulating layer is mounted between the first conductor layer and the second conductor layer. The second circuit board is on the first circuit board, the conducting blocks are respectively mounted in the conducting recesses to electrically connect the first conductor layer and the second conductor layer.
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43.发明授权公开(公告)号：US10371719B2
公开(公告)日：2019-08-06
申请号：US15130982
申请日：2016-04-17
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Chiao-Cheng Chang , Yi-Nong Lin
Abstract: A printed circuit board (PCB) test fixture includes a substrate, a first insulation layer formed on the substrate, a conductor layer formed on the first insulation layer and electrically connected to the upper electrodes through at least one first connection member, a second insulation layer formed on the first insulation layer, and multiple conductive cones arranged on the second insulation layer in a matrix form. A part of the conductive cones is electrically connected to the conductor layer through at least one second connection member. The circuit layout of the conductor layer, the at least one first connection member and the at least one second connection member is employed to supply testing power to a part of the conductive cones and an adjustable arrangement of the conductive cones to enhance density of test probes upon electrical testing.
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公开(公告)号：US20180160533A1
公开(公告)日：2018-06-07
申请号：US15369822
申请日：2016-12-05
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao LIN , Chiao-Cheng CHANG , Yi-Nong LIN
CPC classification number: H05K3/4641 , H05K3/4647 , H05K3/4682 , H05K2201/10242 , H05K2203/041 , H05K2203/0568
Abstract: A multilayer printed circuit board includes a first circuit board, a second circuit board and bonding films. The first circuit board includes a first dielectric layer, a first wiring pattern layer, a plurality of conductive blocks and a plurality of solder balls. The first wiring pattern layer is formed on a first surface of the first dielectric layer and the conductive blocks are formed on a second surface of the first dielectric layer. The solder balls are formed on a surface of the first wiring pattern layer. The second circuit board includes a second dielectric layer, a second wiring pattern layer, second conductive blocks and conductive pillars. The second wiring pattern layer is formed on a third surface of the second dielectric layer and the second conductive blocks are formed on a fourth surface thereof. The conductive pillars are formed on the second wiring pattern layer.
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45.发明授权Method for manufacturing a circuit board with buried element having high density pin count and the circuit board structure 有权用于制造具有高密度引脚数的埋入元件的电路板和电路板结构的方法公开(公告)号：US09439292B1
公开(公告)日：2016-09-06
申请号：US14641016
申请日：2015-03-06
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yi-Fan Kao , Jaen-Don Lan , Yung-Lin Chia , An-Ping Tseng
CPC classification number: H05K3/064 , H01L23/5389 , H05K1/185 , H05K1/188 , H05K3/0008 , H05K3/108 , H05K3/305 , H05K3/425 , H05K2201/09563 , H05K2201/10674 , H05K2203/166
Abstract: A method for manufacturing a circuit board with a buried element having high density pin count, wherein a micro copper window formed in a first circuit by patterned dry film electroplating is easily controlled less than 50 μm so that the micro conduction holes formed after the laser drilling each has a diameter greatly shrunk less than 50 μm so as to highly increase density of the micro conduction holes, thereby facilitating in burial of the buried element with the high density pin count. Additionally, by disposing the micro conduction holes in the same elevation, optically aligning a fixing position for the buried element can be controlled precisely.
Abstract translation: 一种制造具有高密度引脚数的埋入元件的电路板的方法，其中通过图案化干电镀电镀形成在第一电路中的微铜窗容易控制在小于50μm，从而在激光钻孔之后形成的微导电孔 每个具有大大缩小到小于50μm的直径，从而高度增加微通孔的密度，从而便于以高密度引脚数掩埋埋入元件。 此外，通过将相同高度的微通孔设置在一起，可精确地控制掩埋元件的固定位置的光学对准。
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Patent Agency Ranking
46.发明授权公开(公告)号：US09301405B1
公开(公告)日：2016-03-29
申请号：US14604956
申请日：2015-01-26
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yi-Fan Kao , Jaen-Don Lan , Yu-Te Lu , Yung-Lin Chia , An-Ping Tseng
IPC: H01L21/4763 , H05K3/40 , H05K3/06 , H05K3/00 , H05K3/18 , H05K3/02 , H05K1/09 , H05K1/11 , H01L21/48
CPC classification number: H05K3/0035 , H01L21/4857 , H01L2924/01078 , H01L2924/014 , H05K1/115 , H05K3/007 , H05K3/064 , H05K3/421 , H05K3/429 , H05K2201/09536
Abstract: A method for manufacturing microthrough-hole includes electroplating a metal layer on a carrier plate, patterning the metal layer to form a first circuit having copper pads, covering the first circuit with a photoresist layer and not covering the copper window between two of the copper pads, etching the metal layer beneath the copper window and removing the photoresist layer, sequentially forming an insulation layer and a second circuit on the first circuit and the copper window, the second circuit layer having a stop pad corresponding to the copper window, removing the carrier plate, upward drilling through the insulation layer between the stop pad and the copper window to form a microthrough-hole beneath the stop pad, and forming a conductive layer in the microthrough-hole to form the microthrough-hole connecting the first and second circuits. The microthrough-hole and its occupied area is greatly reduced, thereby achieving high circuit density.
Abstract translation: 一种用于制造微通孔的方法包括在载体板上电镀金属层，图案化金属层以形成具有铜焊盘的第一电路，用光致抗蚀剂层覆盖第一电路，并且不覆盖两个铜焊盘之间的铜窗 蚀刻铜窗下方的金属层并除去光致抗蚀剂层，在第一电路和铜窗上依次形成绝缘层和第二电路，第二电路层具有对应于铜窗的停止焊盘，移除载体 通过止动垫和铜窗之间的绝缘层向上钻孔，以在止动垫下方形成微通孔，并在微通孔中形成导电层，形成连接第一和第二电路的微通孔。 微通孔及其占用面积大大降低，从而实现高电路密度。
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公开(公告)号：US08887386B2
公开(公告)日：2014-11-18
申请号：US13663333
申请日：2012-10-29
Applicant: Kinsus Interconnect Technology Corp.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
IPC: H05K3/02
CPC classification number: H05K1/056 , H01L21/4857 , H01L21/486 , H01L23/13 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L2924/0002 , H05K1/0204 , H05K2201/029 , H05K2201/0323 , H05K2201/09054 , H05K2203/0323 , H05K2203/0384 , H05K2203/063 , Y10T29/49117 , Y10T29/49121 , Y10T29/49124 , Y10T29/49155 , Y10T29/49156 , H01L2924/00
Abstract: A method of manufacturing a chip support board structure which includes the steps of forming a metal substrate structure, forming a photo resist pattern, etching the metal substrate structure to form a paddle, removing the photo resist pattern, pressing an insulation layer against the paddle, polishing the insulation layer, forming a circuit layer and forming a solder resist is disclosed. The metal substrate structure is formed by sandwiching a block layer with two metal substrate layers, multilayer. The metal substrate structure is etched under control to an effective depth such that each paddle thus formed has the same shape and depth. Therefore, the method of the present invention can be widely applied to the general mass production processes to effectively solve the problems in the prior arts due to depth differences, such offset, position mismatch and peeling off in the chip support board.
Abstract translation: 一种制造芯片支撑板结构的方法，其包括以下步骤：形成金属基板结构，形成光致抗蚀剂图案，蚀刻金属基板结构以形成桨，去除光致抗蚀剂图案，将绝缘层压靠在桨上， 公开了抛光绝缘层，形成电路层和形成阻焊剂。 金属基板结构是通过将具有两个金属基底层的多层的阻挡层夹在中间而形成的。 在控制下将金属基底结构蚀刻到有效深度，使得如此形成的每个桨具有相同的形状和深度。 因此，本发明的方法可以广泛地应用于通常的批量生产过程，以有效地解决由于芯片支撑板中的深度差异，偏移，位置失配和剥离等现有技术的问题。
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公开(公告)号：US08837808B2
公开(公告)日：2014-09-16
申请号：US13721015
申请日：2012-12-20
Applicant: Kinsus Interconnect Technology Corp.
Inventor： Chia-Chi Lo , Cheng-Hsiung Yang , Jun-Chung Hsu
CPC classification number: H05K1/0269 , H05K3/0008 , H05K3/225 , H05K2201/09927 , H05K2201/09936
Abstract: Disclosed is a method of final defect inspection, including preparing a final defect inspection apparatus which includes a host device, a microscope, a bar code scanner, a support tool and a signal transceiver, using the host device to calibrate an original point in an outline of the circuit board based on a plurality of original mark positions generated by an electromagnetic pen, using the electromagnetic pen to mark each defect position on the inspection region on the circuit board where any defect is found through the microscope, using the signal transceiver to receive and transmit each defect position to the host device, and using the host device to calculate the coordinate of a scrap region based on a relative position between the original point and each defect position so as to generate a shipment file.
Abstract translation: 公开了一种最终缺陷检查的方法，包括使用主机设备准备包括主机，显微镜，条形码扫描仪，支持工具和信号收发器的最终缺陷检查设备来校准轮廓中的原始点 基于由电磁笔产生的多个原始标记位置的电路板，使用电磁笔来标记电路板上通过显微镜发现任何缺陷的检查区域上的每个缺陷位置，使用信号收发器接收 并且将每个缺陷位置发送到主机设备，并且使用主机设备基于原始点和每个缺陷位置之间的相对位置来计算废料区域的坐标，以便生成出货文件。
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公开(公告)号：US20140177939A1
公开(公告)日：2014-06-26
申请号：US13721015
申请日：2012-12-20
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Chia-Chi Lo , Cheng-Hsiung Yang , Jun-Chung Hsu
IPC: G06T7/00
CPC classification number: H05K1/0269 , H05K3/0008 , H05K3/225 , H05K2201/09927 , H05K2201/09936
Abstract: Disclosed is a method of final defect inspection, including preparing a final defect inspection apparatus which includes a host device, a microscope, a bar code scanner, a support tool and a signal transceiver, using the host device to calibrate an original point in an outline of the circuit board based on a plurality of original mark positions generated by an electromagnetic pen, using the electromagnetic pen to mark each defect position on the inspection region on the circuit board where any defect is found through the microscope, using the signal transceiver to receive and transmit each defect position to the host device, and using the host device to calculate the coordinate of a scrap region based on a relative position between the original point and each defect position so as to generate a shipment file.
Abstract translation: 公开了一种最终缺陷检查的方法，包括使用主机设备准备包括主机，显微镜，条形码扫描仪，支持工具和信号收发器的最终缺陷检查设备来校准轮廓中的原始点 基于由电磁笔产生的多个原始标记位置的电路板，使用电磁笔来标记电路板上通过显微镜发现任何缺陷的检查区域上的每个缺陷位置，使用信号收发器接收 并且将每个缺陷位置发送到主机设备，并且使用主机设备基于原始点和每个缺陷位置之间的相对位置来计算废料区域的坐标，以便生成出货文件。
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公开(公告)号：US20140116755A1
公开(公告)日：2014-05-01
申请号：US13663250
申请日：2012-10-29
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
IPC: H05K1/02
CPC classification number: H05K1/0271 , H05K3/4682 , H05K2201/09136 , H05K2201/2018
Abstract: A laminate circuit board structure which includes a first circuit metal layer, a first insulation layer, at least one second circuit metal layer, at least one second insulation layer and a support frame is disclosed. The total thickness of the laminate circuit board structure is less than 150 μm. The support frame provided at the outer edge of the co-plane surface formed by the first circuit metal layer and the first insulation layer does not cover the first circuit metal layer, and is formed of at least one metal material. The support frame provides physical support for the entire board structure without influence on the circuit connection so as to prevent the laminate circuit board structure from warping.
Abstract translation: 公开了一种层叠电路板结构，其包括第一电路金属层，第一绝缘层，至少一个第二电路金属层，至少一个第二绝缘层和支撑框架。 叠层电路板结构的总厚度小于150μm。 设置在由第一电路金属层和第一绝缘层形成的共面的外边缘处的支撑框架不覆盖第一电路金属层，并且由至少一种金属材料形成。 支撑框架为整个板结构提供物理支撑，而不影响电路连接，从而防止层压电路板结构翘曲。
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