公开(公告)号：DE69936611T2

公开(公告)日：2008-05-21

申请号：DE69936611

申请日：1999-05-19

Applicant: ELPIDA MEMORY INC

Inventor： SHIBATA KAYOKO

IPC: G11C7/00 ,  G11C11/41 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409

Abstract: The present invention provides a circuitry for supplying data from a write input/output line pair to a digit line pair for writing the data into memory cells. The circuitry comprises : a balancing device for balancing in voltage level between the write input/output line pair by making a connection of the write input/output line pair ; and a controller connected to the balancing device for controlling balancing operations of the balancing device.

公开(公告)号：DE602004012226D1

公开(公告)日：2008-04-17

申请号：DE602004012226

申请日：2004-12-23

Applicant: HITACHI LTD ,  ELPIDA MEMORY INC

Inventor： HANZAWA SATORU ,  SAKATA TAKESHI ,  KAJIGAYA KAZUHIKO

IPC: G11C11/401 ,  G11C15/04 ,  G11C11/56

Abstract: The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value '1'; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.

公开(公告)号：DE102006041849A1

公开(公告)日：2007-04-12

申请号：DE102006041849

申请日：2006-09-06

Applicant: ELPIDA MEMORY INC

Inventor： ASANO ISAMU ,  SATO NATSUKI ,  NAKAI KIYOSHI

IPC: H01L27/24

公开(公告)号：DE102006035815A1

公开(公告)日：2007-02-22

申请号：DE102006035815

申请日：2006-08-01

Applicant: HITACHI LTD ,  ELPIDA MEMORY INC

Inventor： SEKIGUCHI TOMONORI ,  TAKEMURA RIICHIRO ,  AKIYAMA SATORU ,  HANZAWA SATORU ,  KAJIGAYA KAZUHIKO

IPC: G11C29/52 ,  G11C29/24

Abstract: A semiconductor memory device capable of achieving a sufficient operating margin without increasing an area penalty even in the case of miniaturization is provided. An error correction system composed of a data bit of 64 bits and a check bit of 9 bits is introduced to a memory array such as DRAM, and an error correction code circuit required therein is disposed near a sense amplifier array. In addition to normal memory arrays composed of such memory arrays, a redundant memory array having a sense amplifier array and an error correction code circuit adjacent thereto is provided in a chip. By this means, the error which occurs in the manufacture can be replaced. Also, the error correction code circuit corrects the error at the time of an activate command and stores the check bit at the time of a pre-charge command.

公开(公告)号：DE69733042T2

公开(公告)日：2006-03-02

申请号：DE69733042

申请日：1997-06-05

Applicant: ELPIDA MEMORY INC

Inventor： IKEDA MINARI

IPC: G11C11/409 ,  G11C5/02 ,  G11C7/06 ,  G11C11/401 ,  H01L21/8242 ,  H01L27/108

Abstract: A semiconductor memory device includes a plurality of sense amplifiers which are divided into two groups. There are provided drive wires each extending to an associated one of the sense amplifier groups and being used to independently drive the associated group. The length of each drive wire being thereby reduced up to a half, to operated at a high speed.

公开(公告)号：DE69829039T2

公开(公告)日：2006-02-09

申请号：DE69829039

申请日：1998-12-30

Applicant: ELPIDA MEMORY INC

Inventor： MOCHIDA YOSHIFUMI

IPC: G11C11/407 ,  G11C7/00 ,  G11C7/10

Abstract: A semiconductor storage device (100) having a burst mode capability for accomplishing a rapid pipeline operation is disclosed. A signal delay device (104), such as a first-in-first-out buffer (FIFO), is disposed between the data read circuitry of a memory cell array (102) and an output buffer (106). The signal delay device (104) is composed of a plurality of storage circuits (206-0 and 206-1) connected in parallel. Data values are input to selected of the storage circuits (206-0 and 206-1) by input control signals (DSEL0-DSEL1) and output from selected of the storage circuits (206-0 and 206-1) by output control signals (OSEL0-OSEL1). The DSEL0-DSEL1 and OSEL0-OSEL1 signals are generated in response to count signals (OCNT0-OCNT1).

公开(公告)号：DE102005015789A1

公开(公告)日：2005-11-10

申请号：DE102005015789

申请日：2005-04-06

Applicant: ELPIDA MEMORY INC

Inventor： MICHIMATA SHIGETOMI ,  NAGAI RYO ,  YAMADA SATORU ,  NAKAMURA YOSHITAKA ,  NAKAMURA RYOICHI

IPC: H01L21/28 ,  H01L21/26 ,  H01L21/265 ,  H01L21/283 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/74 ,  H01L21/768 ,  H01L23/52 ,  H01L27/10 ,  H01L29/78

Abstract: A method includes the steps of: implanting boron into a surface region of a silicon substrate to form a p + diffused region; implanting indium into the surface of the p + diffused region, to form an indium-implanted layer; forming a contact metal layer on the indium-implanted layer; and reacting silicon in the silicon substrate including the indium-implanted layer with metal in the contact metal layer to form a titanium silicide layer.

公开(公告)号：DE10326925A1

公开(公告)日：2005-06-16

申请号：DE10326925

申请日：2003-06-13

Applicant: ELPIDA MEMORY INC

Inventor： MATSUI YOSHINORI

IPC: G06F13/16 ,  G06F12/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/406 ,  G11C7/00 ,  G11C11/4063

Abstract: A memory system and a control method for the same enable stable operation at high frequencies without a radiant noise problem. In the memory system, a plurality of DRAMs is provided on each of a plurality of modules, and each DRAM is connected with a memory controller by data lines and clock lines. The clock lines have a topology exclusively applied to each module, while the data lines have a topology for connecting them to their associated DRAMs on each module. Command/address lines also have a topology similar to that of the clock lines. In this case, data signals supplied through the data lines and clock and command/address signals supplied through the clock lines and the command/address lines are transferred at different timings between the DRAMs and the memory controller. For this reason, the DRAMs and the memory controller are provided with circuits for matching the timings.

公开(公告)号：DE102004010649A1

公开(公告)日：2004-11-11

申请号：DE102004010649

申请日：2004-02-28

Applicant: ELPIDA MEMORY INC

Inventor： KIKUCHI WATARU ,  SUGANO TOSHIO ,  ISA SATOSHI

IPC: H01L25/18 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/10 ,  H01L23/50

Abstract: A stacked semiconductor package comprises two semiconductor chips (11, 12) each of which has a mounting surface provided with a plurality of chip pins arranged in a predetermined pattern. The semiconductor chips are mounted on opposite surfaces of a substrate (13) so that the mounting surfaces are faced to each other through the substrate. The substrate is provided with a plurality of package pins formed in an area other than a chip mounting area and arranged in a pattern identical to the predetermined pattern. A pair of the corresponding chip pins of the semiconductor chips are connected to a via formed at an intermediate position therebetween by the use of branch wires equal in length to each other. The via is connected by a common wire to the package pin corresponding to the chip pins connected to the via.

公开(公告)号：DE10242886A1

公开(公告)日：2003-06-05

申请号：DE10242886

申请日：2002-09-16

Applicant: ELPIDA MEMORY INC

Inventor： TAKAI YASUHIRO

IPC: G11C11/407 ,  G06F1/10 ,  G06F1/12 ,  G11C8/00 ,  G11C11/4076 ,  H03K5/13 ,  H03K5/131 ,  H03K5/15 ,  H03L7/081 ,  H03L7/089 ,  H04L7/033

Abstract: Disclosed is an interpolating circuit for producing an output signal having a delay time corresponding to a value obtained by performing interior division of a phase difference between entered first and second signals by a preset interior division ratio. The interpolating circuit includes a waveform synthesis unit and a bias control unit. The waveform synthesis unit includes an OR gate, which receives the first and second signals, for outputting the logic OR between these two signals; a first switch element inserted between a node, which is connected to an output terminal, and a first power supply and turned on and off by the output signal of the OR gate; a series circuit comprising a first constant-current source and a second switch element turned on and off by the first signal; and a series circuit comprising a second constant-current source and a third switch element turned on and off by the second signal; the series circuits being connected in parallel between the output node and a second power supply. On the basis of control signals that decide the interior division ratio, the bias control unit performs control in such a manner that current-path switches are turned on and off so that first and second current values, which are the totals of current values, will flow into the first and second constant-current sources, respectively.