公开(公告)号：US20230325337A1

公开(公告)日：2023-10-12

申请号：US18043479

申请日：2020-08-28

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Chong Bi ,  Ming Liu

IPC: G06F13/40

CPC classification number: G06F13/4063

Abstract: Provided are a data transmission device and a data transmission method, which are applied to a field of an information technology. The data transmission device includes: a signal conversion module (30) and a signal transmission module (20), wherein the signal conversion module (30) is configured to convert, at a data transmitting end, an electrical signal containing a data information into a magnon signal containing the data information; the signal transmission module (20) is configured to transmit the magnon signal containing the data information to a data receiving end; and the signal conversion module (30) is further configured to convert, at the data receiving end, the magnon signal containing the data information into the electrical signal containing the data information. The data transmission method includes transmitting the data by using the magnon signal, and no voltage or current is required in a process of transmitting the data.

公开(公告)号：US20230187497A1

公开(公告)日：2023-06-15

申请号：US17925913

申请日：2021-03-18

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU ,  Xuezheng AI ,  Yongkui ZHANG

IPC: H01L29/06 ,  H01L29/786 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L29/78696 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor apparatus having a staggered structure, a method of manufacturing a semiconductor apparatus, and an electronic device including the semiconductor apparatus. The semiconductor apparatus includes a first element and a second element on a substrate. The first element and the second element each include a comb-shaped structure. The comb-shaped structure includes a first portion extending in a vertical direction relative to the substrate, and at least one second portion extending from the first portion in a lateral direction relative to the substrate and spaced from the substrate. A height of the second portion of the first element in the vertical direction is staggered with respect to a height of the second portion of the second element in the vertical direction. A material of the comb-shaped structure of the first element is different from a material of the comb-shaped structure of the second element.

公开(公告)号：US20230178133A1

公开(公告)日：2023-06-08

申请号：US17966476

申请日：2022-10-14

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yan Cui ,  Jun Luo ,  Meiyin Yang ,  Jing Xu

IPC: G11C11/16 ,  H03K19/20

CPC classification number: G11C11/1697 ,  G11C11/1659 ,  H03K19/20

Abstract: An in-memory computing circuit having reconfigurable logic, including: an input stage and N output stages which are cascaded. The input stage includes 2N STT-MTJs. Each output stage includes STT-MTJs, of which a quantity is equal to a half of a quantity of STT-MTJs in a just previous stage. Two STT-MTJs in the previous stage and one STT-MTJ in the subsequent stage form a double-input single-output in-memory computing unit. Each double-input single-output in-memory computing unit can implement the four logical operations, i.e., NAND, NOR, AND, and OR, under different configurations. Data storage and logical operations can be realized under the same circuit architecture, and reconfigurations among different logic can be achieved.

公开(公告)号：US20230163204A1

公开(公告)日：2023-05-25

申请号：US17919652

申请日：2021-03-23

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU ,  Chen LI

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/0676 ,  H01L29/6653 ,  H01L29/66545

Abstract: Disclosed are a semiconductor device having a U-shaped structure, a method of manufacturing the semiconductor device, and an electronic including the semiconductor device. According to an embodiment, the semiconductor device may include: a first fin and a second fin disposed opposite to each other, wherein the first fin and the second fin extend in a vertical direction with respect to a substrate; a connection nanosheet connecting a bottom end of the first fin to a bottom end of a second fin to form a U-shaped structure, wherein the connection nanosheet is spaced apart from a top surface of the substrate.

公开(公告)号：US20230162007A1

公开(公告)日：2023-05-25

申请号：US17753140

申请日：2021-02-22

Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES

Inventor： Feng ZHANG ,  Qiang HUO

IPC: G06N3/0464 ,  G06N3/065

CPC classification number: G06N3/0464 ,  G06N3/065

Abstract: The present disclosure discloses a method and apparatus for convolution operation of a convolutional neural network. The method comprises acquiring input voltages used for characterizing pixel values; when the input voltages are scanned through convolutional sliding windows, obtaining times of reusing of the input voltages in the convolutional sliding windows; grouping the input voltages based on a difference in the times of reusing of the input voltages; extracting the input voltages in same groups once and performing convolution calculation with convolution kernels respectively, to obtain a result corresponding to each group; obtaining a result of convolution operation based on the result corresponding to each group, to implement convolution operation in the convolutional neural network. The present disclosure reduces energy consumption during convolution operations effectively.

公开(公告)号：US20220416808A1

公开(公告)日：2022-12-29

申请号：US17422050

申请日：2021-06-04

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Kunyu WANG ,  Li ZHOU ,  Jie CHEN ,  Minghui CHEN ,  Ming CHEN ,  Wenjing XU ,  Chengbin ZHANG

IPC: H03M3/00

Abstract: A quantizer for a sigma-delta modulator, a sigma-delta modulator, and a method of shaping noise are provided. The quantizer includes: an integrator configured to generate, in a Kth sampling period, a quantization error signal for a Kth period according to an internal signal, a quantization error signal for a (K−1)th period, a filtered quantization error signal for the (K−1)th period and a filtered quantization error signal for a (K−2)th period; an integrating capacitor configured to store the quantization error signal for the Kth period, to weight the internal signal in a (K+1)th sampling period; a passive low-pass filter configured to acquire the quantization error signal for the Kth period in a Kth discharge period, and feed back the filtered quantization error signal to the integrator in a (K+1)th sampling period and a (K+2)th sampling period; and a comparator configured to quantize the quantization error signal for the Kth period.

公开(公告)号：US11532756B2

公开(公告)日：2022-12-20

申请号：US17112903

申请日：2020-12-04

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

Abstract: A C-shaped active area semiconductor device and a method of manufacturing the same and electronic device including the semiconductor device are provided. According to embodiments, the semiconductor device includes: a channel portion extending vertically on a substrate; source/drain portions located at upper and lower ends of the channel portion relative to the substrate and along the channel portion, wherein the source/drain portion extends toward a side of the channel portion in a lateral direction relative to the substrate, so that the source/drain portions and the channel portion constitute a C-shaped structure; a gate stack that overlaps the channel portion on an inner sidewall of the C-shaped structure, wherein the gate stack has a portion surrounded by the C-shaped structure; and a back gate stack overlapping the channel portion on an outer sidewall of the C-shaped structure.

公开(公告)号：US20220352351A1

公开(公告)日：2022-11-03

申请号：US17661178

申请日：2022-04-28

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234

Abstract: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the device. According to the embodiments, the semiconductor device may include: an active region extending substantially in a vertical direction on a substrate; a gate stack formed around at least a portion of an outer periphery of a middle section of the active region in the vertical direction, wherein the active region comprises a channel region opposite to the gate stack, and a first source/drain region and a second source/drain region located on two opposite sides of the channel region in the vertical direction; a first spacer located between a conductor layer of the gate stack and the first source/drain region, and a second spacer located between the conductor layer of the gate stack and the second source/drain region.

公开(公告)号：US20220310510A1

公开(公告)日：2022-09-29

申请号：US17836934

申请日：2022-06-09

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: An interconnection structure and a method of manufacturing the same, and an electronic device including the interconnection structure are provided. According to an embodiment, the interconnection structure includes: a first interconnection line at a first level, including at least a first portion extending along a first direction; a second interconnection line at a second level higher than the first level, including at least a second portion extending along a second direction crossing the first direction; a via plug disposed between the first portion of the first interconnection line and the second portion of the second interconnection line, and configured to electrically connect the first interconnection line and the second interconnection line, wherein the via plug includes a first pair of sidewalls respectively extending substantially parallel to corresponding sidewalls of the first portion and a second pair of sidewalls respectively extending substantially parallel to corresponding sidewalls of the second portion.

公开(公告)号：US20220285506A1

公开(公告)日：2022-09-08

申请号：US17653774

申请日：2022-03-07

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu

IPC: H01L29/417 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11587 ,  H01L27/11597 ,  H01L29/08 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792

Abstract: A NOR-type storage device, a method of manufacturing the same, and an electronic apparatus including the same are provided. The NOR-type storage device includes: a gate stack extending vertically on a substrate; an active region surrounding a periphery of the gate stack, the active region including first and second source/drain regions, a first channel region between the first and second source/drain regions, third and fourth source/drain regions, and a second channel region between the third and fourth source/drain regions; first, second, third and fourth interconnection layers extending laterally from the first to fourth source/drain regions, respectively; and a source line contact part extending vertically with respect to the substrate to pass through the first to fourth interconnection layers and electrically connected to one of the first interconnection layer and the second interconnection layer, and to one of the third interconnection layer and the fourth interconnection layer.