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公开(公告)号：US20230178133A1
公开(公告)日：2023-06-08
申请号：US17966476
申请日：2022-10-14
Inventor： Yan Cui , Jun Luo , Meiyin Yang , Jing Xu
CPC classification number: G11C11/1697 , G11C11/1659 , H03K19/20
Abstract: An in-memory computing circuit having reconfigurable logic, including: an input stage and N output stages which are cascaded. The input stage includes 2N STT-MTJs. Each output stage includes STT-MTJs, of which a quantity is equal to a half of a quantity of STT-MTJs in a just previous stage. Two STT-MTJs in the previous stage and one STT-MTJ in the subsequent stage form a double-input single-output in-memory computing unit. Each double-input single-output in-memory computing unit can implement the four logical operations, i.e., NAND, NOR, AND, and OR, under different configurations. Data storage and logical operations can be realized under the same circuit architecture, and reconfigurations among different logic can be achieved.
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公开(公告)号：US11930720B2
公开(公告)日：2024-03-12
申请号：US17495390
申请日：2021-10-06
Inventor： Meiyin Yang , Jun Luo , Yan Cui , Jing Xu
CPC classification number: H10N52/80 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/18 , G11C11/22 , H10B61/00 , H10N52/00 , G11C11/1659
Abstract: The present disclosure provides a storage unit, a data writing method and a data reading method thereof, a memory and an electronic device. The storage unit includes a semiconductor substrate, a first insulating medium layer, a ferroelectric thin film layer, a bottom electrode, a tunnel junction, a first metal interconnection portion, a second metal interconnection portion, a third metal interconnection portion and a fourth metal interconnection portion. The first insulating medium layer is formed on the semiconductor substrate, the ferroelectric thin film layer is disposed on the first insulating medium layer, the bottom electrode is formed on the ferroelectric thin film layer, and the tunnel junction is formed on the bottom electrode. The first metal interconnection portion is connected to a first end of the bottom electrode, and the third metal interconnection portion is connected to a second end of the bottom electrode. The second metal interconnection portion is connected to the ferroelectric thin film layer, and the fourth metal interconnection portion is connected to the tunnel junction. As compared with the prior art, the present disclosure can control a directional flipping of the magnetic moment in the tunnel junction based on the ferroelectric thin film layer provided. Based on the structural design of the storage unit, the present disclosure does not require an external magnetic field, and fully meets the requirement of high integration of the device.
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公开(公告)号：US10991877B2
公开(公告)日：2021-04-27
申请号：US16560357
申请日：2019-09-04
Inventor： Meiyin Yang , Jun Luo , Sumei Wang , Jing Xu , Yanru Li , Junfeng Li , Yan Cui , Wenwu Wang , Tianchun Ye
Abstract: A multi-state memory and a method for manufacturing the same. A magnetoresistive tunnel junction is disposed on a spin-orbit coupling layer, and thermal annealing is performed after dopant ions are injected from a side of the magnetoresistive tunnel junction. The concentration of dopant ions in the magnetoresistive tunnel junction has a gradient variation along the direction that is perpendicular to the direction of the current and within the plane in which the spin-orbit coupling layer is located. Symmetry along the direction perpendicular to the direction of the current is broken. In a case a current flows into the spin-orbit coupling layer, resistance are outputted in multiple states in linearity with the current. The multi-state storage is achieved. It can meet a requirement on hardware of neural network synapses, and is applicable to calculation in a neural network.
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公开(公告)号：US12198746B2
公开(公告)日：2025-01-14
申请号：US17966476
申请日：2022-10-14
Inventor： Yan Cui , Jun Luo , Meiyin Yang , Jing Xu
Abstract: An in-memory computing circuit having reconfigurable logic, including: an input stage and N output stages which are cascaded. The input stage includes 2N STT-MTJs. Each output stage includes STT-MTJs, of which a quantity is equal to a half of a quantity of STT-MTJs in a just previous stage. Two STT-MTJs in the previous stage and one STT-MTJ in the subsequent stage form a double-input single-output in-memory computing unit. Each double-input single-output in-memory computing unit can implement the four logical operations, i.e., NAND, NOR, AND, and OR, under different configurations. Data storage and logical operations can be realized under the same circuit architecture, and reconfigurations among different logic can be achieved.
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