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公开(公告)号：KR101660491B1
公开(公告)日：2016-09-27
申请号：KR1020100032801
申请日：2010-04-09
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L27/108
CPC classification number: H01L27/11548 , H01L27/11519 , H01L27/11529
Abstract: 본발명은반도체장치및 그제조방법을제공한다. 이장치는, 셀어레이영역의측면과상부에각각배치되는수소차단패턴들을포함함으로써, 수소가셀 어레이영역안으로확산되는것을방지할수 있다. 이로써, 수소가터널절연막등 내에트랩되지않아반도체장치의신뢰성을향상시킬수 있다. 또한본 발명의반도체장치의제조방법에서는셀 어레이콘택플러그를형성할때 측면수소차단패턴과상부수소차단패턴을동시에만들기때문에, 수소차단패턴의형성을위한별도의추가공정을필요로하지않아공정을단순화시킬수 있다.
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公开(公告)号：KR1020160106822A
公开(公告)日：2016-09-13
申请号：KR1020150029194
申请日：2015-03-02
Applicant: 삼성전자주식회사
CPC classification number: G09G5/006 , G09G2300/0426 , G09G2310/0289 , G09G2330/021 , G09G2380/02 , H02M3/07 , H02M3/073 , H02M2001/0032 , H02M2003/075 , Y02B70/16 , G09G3/20 , G09G3/36
Abstract: 본발명의실시예에따르면, 표시패널에포함된복수의게이트라인들을구동하는디스플레이구동회로가제공된다. 디스플레이구동회로는외부전원으로부터의전압을승압하여출력전압을출력하는전하펌프; 및출력전압을기반으로복수의게이트라인들을구동하는게이트라인드라이버를포함하고, 표시패널의구동전류가소정의레벨이상인경우, 전하펌프는고전류모드로동작하고, 표시패널의구동전류가소정의레벨이하인경우전하펌프는저전류모드로동작한다.
Abstract translation: 根据本发明的实施例，提供了驱动显示面板中包括的多个栅极线的显示驱动电路。 显示驱动电路包括：电荷泵，被配置为升高来自外部电源的电压以输出输出电压; 以及栅极线驱动器，被配置为基于所述输出电压来驱动所述多条栅极线。 当显示面板的驱动电流处于预定电平以上时，电荷泵以高电流模式工作。 当显示面板的驱动电流处于预定电平或更低时，电荷泵以低电流模式工作。 因此，显示驱动电路具有改进的性能。
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公开(公告)号：KR101650722B1
公开(公告)日：2016-08-24
申请号：KR1020100012823
申请日：2010-02-11
Applicant: 삼성전자주식회사
IPC: H01L33/20
Abstract: 본발명은텍스쳐(texture) 효과를통해광추출효율(Light Extraction Efficiency)이향상된질화물반도체발광소자에관한것으로, 기판위에형성되며, 제1 도전형질화물반도체층및 제2 도전형질화물반도체층과, 그사이에위치하는활성층을포함하는발광구조물; 상기제1 도전형질화물반도체층에전기적으로연결된제1 전극; 상기제2 도전형질화물반도체층에전기적으로연결된제2 전극; 및상기제1 전극및 상기제2 전극사이에위치하며, 상기발광구조물의상하면을관통하도록형성된복수개의관통홀을구비하는광추출패턴;을포함한다.
Abstract translation: 的通过影响萃取效率（光提取效率）的增强的氮化物涉及一种半导体发光器件，形成一基板，一第一导电型氮化物半导体层和所述第二导电型氮化物半导体层上的本发明的纹理（质地）; 包括位于其间的有源层的发光结构; 电连接到第一导电材料半导体层的第一电极; 电连接到第二导电材料半导体层的第二电极; 并且光提取图案设置在第一电极和第二电极之间，光提取图案具有形成为穿透发光结构的下表面的多个通孔。
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公开(公告)号：KR1020130120800A
公开(公告)日：2013-11-05
申请号：KR1020120043958
申请日：2012-04-26
Applicant: 삼성전자주식회사
CPC classification number: H01L33/60 , H01L33/04 , H01L33/642 , H05K1/0206
Abstract: A light emitting device package according to the present performance type comprises; a light emitting device which is mounted on a substrate and is connected to an electrode pattern; a heat radiation part which is positioned on the lower part of the light emitting device and discharges a heat of the light emitting device to the lower part of the substrate; a reflecting part which is placed between the light emitting device and the heat radiation part and reflects light generated in the light emitting device to outside.
Abstract translation: 根据本发明的性能类型的发光器件封装包括： 发光装置，其安装在基板上并连接到电极图案; 放热部，其位于所述发光元件的下部，将所述发光元件的热量排出到所述基板的下部; 反射部分，放置在发光器件和散热部分之间，并将在发光器件中产生的光反射到外部。
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公开(公告)号：KR1020120042500A
公开(公告)日：2012-05-03
申请号：KR1020100104215
申请日：2010-10-25
Applicant: 삼성전자주식회사
CPC classification number: H01L33/005 , H01L33/32 , H01L33/38 , H01L33/405 , H01L33/42 , H01L2933/0016 , H01L2933/0058 , H01L2933/0066
Abstract: PURPOSE: A semiconductor light emitting device and a manufacturing method thereof are provided to improve light extraction efficiency by arranging an insulating layer and a reflection part on a light emitting structure. CONSTITUTION: A light emitting structure(6) is formed on a substrate(2). The light emitting structure comprises a first conductivity type semiconductor layer(3), an active layer(4), and a second conductivity type semiconductor layer(5). An insulating layer(7) is formed on the upper surface of the second conductivity type semiconductor layer. A reflection part(9) is formed on the insulating layer. A first electrode(10) is formed on the first conductivity type semiconductor layer. A second electrode(11) is formed on the reflection part.
Abstract translation: 目的：提供半导体发光器件及其制造方法，以通过在发光结构上设置绝缘层和反射部分来提高光提取效率。 构成：在基板（2）上形成发光结构（6）。 发光结构包括第一导电类型半导体层（3），有源层（4）和第二导电类型半导体层（5）。 绝缘层（7）形成在第二导电类型半导体层的上表面上。 反射部（9）形成在绝缘层上。 第一电极（10）形成在第一导电类型半导体层上。 第二电极（11）形成在反射部分上。
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Patent Agency Ranking
公开(公告)号：KR1020110093037A
公开(公告)日：2011-08-18
申请号：KR1020100012823
申请日：2010-02-11
Applicant: 삼성전자주식회사
IPC: H01L33/20
Abstract: PURPOSE: A nitride semiconductor light emitting device is provided to use a light extraction pattern which is formed by eliminating layers from a semiconductor layer until an active layer is eliminated, thereby increasing light extraction efficiency. CONSTITUTION: A light emitting structure is formed on a substrate(110). The light emitting structure includes a first conductive nitride semiconductor layer(120), an active layer(130), and a second conductive nitride semiconductor layer(140). A first electrode(150) is electrically connected to the first conductive nitride semiconductor layer. A second electrode(160) is electrically connected to the second conductive nitride semiconductor layer. A light extraction pattern(170) has a through hole.
Abstract translation: 目的：提供一种氮化物半导体发光器件，以使用通过从半导体层去除层直到消除有源层而形成的光提取图案，从而提高光提取效率。 构成：在基板（110）上形成发光结构。 发光结构包括第一导电氮化物半导体层（120），有源层（130）和第二导电氮化物半导体层（140）。 第一电极（150）电连接到第一导电氮化物半导体层。 第二电极（160）电连接到第二导电氮化物半导体层。 光提取图案（170）具有通孔。
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公开(公告)号：KR1020110069375A
公开(公告)日：2011-06-23
申请号：KR1020090126084
申请日：2009-12-17
Applicant: 삼성전자주식회사
IPC: H01L33/62
CPC classification number: H01L2224/24137 , H01L2224/48137 , H01L2224/73267 , H01L2224/82 , H01L2224/92244 , H01L27/156 , H01L33/0008 , H01L33/62 , H01L2933/0033
Abstract: PURPOSE: A light emitting diode array and a manufacturing method thereof are provided to improve stability and reliability by preventing a contact between a bridge wiring and a light emitting diode cell. CONSTITUTION: A plurality of light emitting diode cells(C1,C2) are formed on a substrate(101). A light emitting diode cell includes a first conductive semiconductor layer(102), an active layer(103), and a second conductive semiconductor layer(104). A wiring structure between light emitting diode cells is a bridge wire(105). The bridge wire is separated from the top of the substrate and the side of the light emitting diode cell. An air gap(107) is interposed between the bridge wire and the substrate.
Abstract translation: 目的：提供一种发光二极管阵列及其制造方法，以通过防止桥接布线和发光二极管单元之间的接触来提高稳定性和可靠性。 构成：在基板（101）上形成多个发光二极管单元（C1，C2）。 发光二极管单元包括第一导电半导体层（102），有源层（103）和第二导电半导体层（104）。 发光二极管单元之间的布线结构是桥接线（105）。 桥接线与衬底的顶部和发光二极管单元的侧面分离。 气隙（107）插入在桥接线和衬底之间。
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公开(公告)号：KR1020020065113A
公开(公告)日：2002-08-13
申请号：KR1020010005460
申请日：2001-02-05
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247 , H01L29/788
Abstract: PURPOSE: A method for fabricating a NAND type flash memory is provided to alleviate problems of mis-alignment and reduce the number of total processes by using a self-alignment method. CONSTITUTION: A gate pattern is formed by laminating a gate oxide layer(11), a floating gate layer(13), an ONO dielectric layer(15), a control gate layer(17), a silicon nitride layer(51), and a capping layer on a substrate of a NAND flash memory cell and a butting contact portion. The silicon nitride layer(51) is removed from the butting contact portion by performing a patterning process. A silicon nitride layer is deposited on a whole surface of the substrate. A sidewall spacer(71) is formed by etching the silicon nitride layer. An interlayer dielectric(81) is laminated on the whole surface of the substrate. A photoresist layer(91) is formed thereon. A trench and a contact hole are formed by etching the interlayer dielectric(81). A trench(73') is formed on the cell region and a butting contact hole(75') is formed on the butting contact portion by performing the etch process, continuously.
Abstract translation: 目的：提供一种制造NAND型闪速存储器的方法，以减轻误配对的问题，并通过使用自对准方法减少总工艺数量。 构成：通过层叠栅极氧化物层（11），浮动栅极层（13），ONO电介质层（15），控制栅极层（17），氮化硅层（51）和 NAND闪存单元的衬底上的覆盖层和对接接触部分。 通过进行图案化处理，从对接接触部去除氮化硅层（51）。 在衬底的整个表面上沉积氮化硅层。 通过蚀刻氮化硅层形成侧壁间隔物（71）。 在基板的整个表面上层叠层间电介质（81）。 在其上形成光致抗蚀剂层（91）。 通过蚀刻层间电介质（81）形成沟槽和接触孔。 在单元区域上形成沟槽（73'），并且通过连续执行蚀刻工艺在对接部分上形成对接接触孔（75'）。
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公开(公告)号：KR1020010047845A
公开(公告)日：2001-06-15
申请号：KR1019990052231
申请日：1999-11-23
Applicant: 삼성전자주식회사
Inventor： 김재윤
IPC: G06F7/50
Abstract: PURPOSE: A binary adder selecting a carry is provided to enhance a calculating velocity by selecting with respect to a carry transmission from the least significant bit to the most significant bit rapidly. CONSTITUTION: A PK generator(10) comprises eight blocks(BYTE0¯BYTE7), and each block receives an addend(A) and a summand(B) by 8-bit. The PK generator(10) generates propagation signals(P(63:0)) and kill signals(K(63:0)). A manchester carry chain(20) receives the propagation signals(P) and kill signals(K) and generates a group transmission signal(P70(7:0)), a partial deletion signal(K74(7:0)) and a group deletion signal(K70(7:0)). A local carry chain(30) receives the propagation signals(P) and kill signals(K) from the PK generator(10) and outputs a carry output signal(C0(63:0)) as a carry signal of the lower bit is '0' and outputs a carry output signal(C1(63:0)) as a carry signal of the lower bit is '1'. A byte carry generator(40) receives the group transmission signal(P70(7:0)), a partial deletion signal(K74(7:0)) and a group deletion signal(K70(7:0)) from the manchester carry chain(20) and generates a carry selection signal(CIN_BYTE(7:0)) displaying whether the carries created in each block is transmitted to the upper block. A carry selecting and adding circuit(50) responses to the carry selection signal(CIN_BYTE(7:0)) and selects one signal out of carry signals(C0,C1) inputted from the local carry chain(30). The carry selecting and adding circuit(50) outputs an added signal(S(63:0)) by performing exclusively OR of a transmission signal inputted from the PK generator(10).
Abstract translation: 目的：提供选择进位的二进制加法器，通过相对于从最低有效位到最高有效位的进位传输进行快速选择来增强计算速度。 构成：PK发生器（10）包括八个块（BYTE0〜BYTE7），每个块通过8位接收加法（A）和加法器（B）。 PK发生器（10）产生传播信号（P（63：0））和杀死信号（K（63：0））。 曼彻斯特携带链（20）接收传播信号（P）和杀死信号（K），并生成组发送信号（P70（7：0）），部分删除信号（K74（7：0））和组 删除信号（K70（7：0））。 本地进位链（30）从PK发生器（10）接收传播信号（P）和停止信号（K），并输出进位输出信号（C0（63：0）），作为低位的进位信号 '0'，并输出进位输出信号（C1（63：0））作为低位的进位信号为'1'。 字节进位发生器（40）从曼彻斯特携带中接收组发送信号（P70（7：0）），部分删除信号（K74（7：0））和组删除信号（K70（7：0）） 链路（20），并且生成显示每个块中创建的载体是否被发送到上部块的进位选择信号（CIN_BYTE（7：0））。 对进位选择信号（CIN_BYTE（7：0））作出响应的进位选择和加法电路（50），并从从本地进位链（30）输入的进位信号（C0，C1）中选择一个信号。 进位选择和加法电路（50）通过执行从PK发生器（10）输入的发送信号的异或来输出相加信号（S（63：0））。
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公开(公告)号：KR1019990051357A
公开(公告)日：1999-07-05
申请号：KR1019970070674
申请日：1997-12-19
Applicant: 삼성전자주식회사
Inventor： 김재윤
IPC: G06F15/00
Abstract: 수퍼스칼라 프로세서의 다중 분기 예측 장치가 개시된다. 이 수퍼스칼라 프로세서의 다중 분기 예측 장치는, 소정 명령 버퍼에 저장된 제1분기 명령과 제2분기 명령의 인덱스를 입력하고, 각 인덱스를 저장하는 로칼 히스토리 테이블, 로컬 히스토리 테이블에 저장된 제1분기 명령의 인덱스와 제2분기 명령의 인덱스를 입력하여 제1분기 예측 값과 제2분기 예측값을 생성하는 로칼 예측 수단, N(>0)개의 레지스터를 구비하고, N개의 레지스터는 각각 한 사이클 라인 상의 제1분기 명령의 경로 히스토리 정보와, 경로 히스토리의 1비트 쉬프트된 히스토리 값에 소정 비트를 부가한 히스토리 정보를 저장하는 글로벌 히스토리 레지스터, 글로벌 히스토리 레지스터에 저장된 히스토리 정보를 입력하여 N개의 글로벌 예측 값을 생성하는 글로벌 예측 수단, 로컬 예측 수단의 예측 값과 글로벌 예측 수단의 예측값 중 하나를 예측 선택 신호로서 출력하는 예측 선택 제어 수단, 예측 선택 신호에 응답하여 로컬 예측 수단의 예측값과 글로벌 예측 수단의 예측 값을 선택적으로 출력하는 예측 선택 수단, 예측 선택 수단에서 출력된 I번째 분기 명령의 마지막 예측 값과, J번째 분기 명령의 마지막 예측 값에 응답하여 분기 목표 어드레스를 생성하는 예측 어드레스 발생 수단, 예측된 목표 어드레스에 상응하는 명령을 인출하는 명령 인출 수단을 구비하는 것을 특징으로한다.
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