公开(公告)号：KR101286238B1

公开(公告)日：2013-07-15

申请号：KR1020070077477

申请日：2007-08-01

Applicant: 삼성전자주식회사

Inventor： 정회주 ,  최주선 ,  임수억

IPC: G06F13/14 ,  G06F11/08

CPC classification number: H03M13/091 ,  H03M13/6575

Abstract: 본 발명은 데이터 병렬화 수신기를 공개한다. 이 장치는 본 발명의 데이터 병렬화 수신기는 외부로부터 패킷 형태로 인가되는 직렬 데이터를 인가받아 샘플링하고 입력되는 순서에 따라 정렬시켜 병렬 데이터로 변환하여 출력하는 입력 신호 수신부, 병렬 데이터를 인가받아 입력되는 순서에 따라 그룹화하여 각 그룹별로 부분적 CRC 계산을 수행하여 복수개의 부분적 CRC 계산 결과를 순차적으로 출력하는 CRC 부분 계산부, 복수개의 부분적 CRC 계산 결과를 인가받아 조합하여 CRC 계산 데이터를 출력하는 CRC 부분 계산 병합부를 구비하는 것을 특징으로 한다. 따라서, 본 발명에 의할 경우 명령어가 입력되는 순서에 따라 시간상 적응적으로 CRC 계산 데이터를 생성하여 CRC 데이터 오류 검출에 소요되는 시간을 단축함으로써 고속의 데이터 전송 속도가 요구되는 데이터 수신기의 성능을 개선할 수 있고, 병렬 처리되어질 입력 데이터의 크기가 증가할지라도 회로 설계상의 효율성을 증대시킬 수 있다.
병렬화 수신기, 데이터 오류의 정정, CRC 계산

公开(公告)号：KR1020130068915A

公开(公告)日：2013-06-26

申请号：KR1020110136365

申请日：2011-12-16

Applicant: 삼성전자주식회사

Inventor： 유학수 ,  최주선 ,  황홍선

IPC: G11C11/4096 ,  G11C7/10

CPC classification number: G06F12/00 ,  G06F13/16 ,  G06F13/1668 ,  G11C11/406

Abstract: PURPOSE: A memory system and an operation control method thereof are provided to effectively perform refresh and reading operations by independently managing a weak memory cell and a normal memory cell. CONSTITUTION: A memory device(100) includes a plurality of memory cells and a first storage unit(180). The first storage unit stores information of a weak cell among the plurality of memory cells. A memory controller(200) transmits an operation command signal related to the memory cell operation to the memory device, receives the information of the weak cell from the first storage unit, and controls the operation of the memory device. The memory device transmits the information of the weak cell to the memory controller when the operation command signal is transmitted to the memory controller and the memory cell corresponding to the operation command cell is the weak cell. [Reference numerals] (180) First storage unit; (182) Buffer; (190) Data input and output unit; (210) Command generating unit; (220) I/O buffer; (230) Control unit; (240) Second storage unit

Abstract translation: 目的：提供一种存储器系统及其操作控制方法，以通过独立地管理弱存储器单元和正常存储单元来有效地执行刷新和读取操作。 构成：存储装置（100）包括多个存储单元和第一存储单元（180）。 第一存储单元存储多个存储单元中的弱单元的信息。 存储器控制器（200）将与存储器单元操作相关的操作命令信号发送到存储器件，从第一存储单元接收弱单元的信息，并控制存储器件的操作。 当操作命令信号被发送到存储器控制器时，存储器件将弱信号的信息发送到存储器控制器，并且与操作命令单元相对应的存储单元是弱单元。 （附图标记）（180）第一存储单元; （182）缓冲液 （190）数据输入输出单元; （210）指令发生单元; （220）I / O缓冲器; （230）控制单元; （240）第二存储单元

公开(公告)号：KR1020120132278A

公开(公告)日：2012-12-05

申请号：KR1020110092219

申请日：2011-09-09

Applicant: 삼성전자주식회사

Inventor： 박철성 ,  최주선

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0688 ,  G11C7/10 ,  G11C8/10 ,  G11C11/56 ,  G11C11/5607 ,  G11C11/5621 ,  G11C11/565 ,  G11C11/5678 ,  G11C11/5685 ,  G11C2211/5641 ,  G11C2213/71

Abstract: PURPOSE: A memory chip, a memory system, and a method for accessing the memory chip are provided to implement the optimum storage capacity by including sub storage units with different storage capacities in one memory chip. CONSTITUTION: A storage unit(STU) forms a storage region with a preset capacity between a first standard capacity and a second standard capacity. The second standard capacity is twice larger than the first standard capacity. A control unit(COU) controls data writing and reading operations in the storage unit. A storage unit includes a first sub storage unit and a second sub storage unit. The first sub storage unit is activated in response to a first selection signal and has a third standard capacity. A second sub storage unit is activated in response to a second selection signal and has a fourth standard capacity. [Reference numerals] (COU) Control unit; (STU) Storage unit(2^n

Abstract translation: 目的：提供一种存储器芯片，存储器系统和用于访问存储器芯片的方法，以通过在一个存储器芯片中包括具有不同存储容量的子存储单元来实现最佳存储容量。 构成：存储单元（STU）形成具有在第一标准容量和第二标准容量之间的预设容量的存储区域。 第二标准容量是第一标准容量的两倍。 控制单元（COU）控制存储单元中的数据写入和读取操作。 存储单元包括第一子存储单元和第二子存储单元。 第一子存储单元响应于第一选择信号被激活并且具有第三标准容量。 第二子存储单元响应于第二选择信号被激活并且具有第四标准容量。 （附图标记）（COU）控制单元; （STU）存储单元（2 ^ n

公开(公告)号：KR1020120024026A

公开(公告)日：2012-03-14

申请号：KR1020100086580

申请日：2010-09-03

Applicant: 삼성전자주식회사

Inventor： 강욱성 ,  전영현 ,  최주선

IPC: G11C5/02 ,  G11C7/10 ,  H01L25/18

CPC classification number: H01L25/18 ,  G11C5/02 ,  G11C7/10 ,  H01L2224/48091 ,  H01L2225/06544 ,  G11C5/025 ,  H01L2924/00014

Abstract: PURPOSE: A semiconductor memory device is provided to implement an optimized interface by differently setting input and output methods of an inner input and output unit and an outer input and output unit according to a data rate of each through electrode. CONSTITUTION: An inner input and output unit(IIO) includes a plurality of through electrodes. The number of through electrodes is changed according to a first input and output method. An outer input and output unit(OIO) transmits data outputted from a first semiconductor memory chip and a second semiconductor memory chip to the outside with a second input and output type. An interface control circuit(ICC) includes an input and output interface unit. The input and output interface unit interfaces transmission and reception of data between the inner input and output unit of the first input and output type and the outer input and output unit of the second input and output type.

Abstract translation: 目的：提供一种半导体存储器件，以通过根据每个通孔的数据速率不同地设置内部输入和输出单元以及外部输入和输出单元的输入和输出方法来实现优化的接口。 构成：内部输入和输出单元（IIO）包括多个通孔。 通过电极的数量根据第一输入和输出方法而改变。 外部输入和输出单元（OIO）以第二输入和输出类型将从第一半导体存储器芯片和第二半导体存储器芯片输出的数据发送到外部。 接口控制电路（ICC）包括输入和输出接口单元。 输入和输出接口单元接收第一输入和输出类型的内部输入和输出单元之间的数据的发送和接收以及第二输入和输出类型的外部输入和输出单元。

公开(公告)号：KR100770703B1

公开(公告)日：2007-10-29

申请号：KR1020060082619

申请日：2006-08-30

Applicant: 삼성전자주식회사

Inventor： 최주선 ,  정회주

IPC: G11C5/14

CPC classification number: G06F1/3203 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

Abstract: A memory system with a power throttling scheme based on a power parameter of a memory device is provided to enable optimum power control by controlling power throttling on the ground of power characteristics information of the memory device. A memory device(200) is set as a specific power characteristics mode through a mode register set command, and provides the set power characteristics information. A memory controller(100) transmits the mode register set command to the memory device, and reads the power characteristics information of the set power characteristics mode, and generates power control information on the ground of the read power characteristics information, and makes a command generation schedule in response to the power control information, and provides a command to the memory device by the command schedule. The memory device comprises a mode register for storing mode setting information, and a power register stored with power characteristics information table on the ground of the mode setting information, and an interface part providing the power characteristics information in response to a power characteristics information request command.

Abstract translation: 提供具有基于存储器件的功率参数的功率节流方案的存储器系统，以通过控制基于存储器件的功率特性信息的功率节流来实现最佳功率控制。 通过模式寄存器设置命令将存储器件（200）设置为特定功率特性模式，并提供设定功率特性信息。 存储器控制器（100）将模式寄存器设置命令发送到存储器件，并读取设置的功率特性模式的功率特性信息，并且基于读取功率特性信息生成功率控制信息，并且产生命令生成 响应于功率控制信息调度，并且通过命令调度向存储器件提供命令。 存储装置包括用于存储模式设置信息的模式寄存器和存储有基于模式设置信息的功率特性信息表的功率寄存器，以及响应于功率特性信息请求命令提供功率特性信息的接口部分 。

公开(公告)号：KR1020070089387A

公开(公告)日：2007-08-31

申请号：KR1020060019343

申请日：2006-02-28

Applicant: 삼성전자주식회사

Inventor： 김재관 ,  최주선

IPC: H03K19/0175

CPC classification number: H03K19/0005 ,  H04L25/0278 ,  H04L25/0288

Abstract: A dynamic output buffer circuit is provided to perform an automatic impedance matching and a pre-emphasis by a circuit installed inside a chip when appropriately selecting a test circuit. A dynamic output buffer circuit includes a controlling circuit(410) and an output circuit(420). The controlling circuit(410) includes a pre-emphasis circuit, an impedance matching circuit, and a register circuit. The controlling circuit(410) matches the characteristic impedance of a metal line with the output impedance of a dynamic output circuit. The output circuit(420) includes a dynamic ODT(430) and an input stage(440). The output circuit(420) outputs at least one output signal(D/O) controlling the output impedance and performing pre-emphasis to at least one input signal(D/I).

Abstract translation: 提供动态输出缓冲电路，以在适当选择测试电路时执行安装在芯片内部的电路的自动阻抗匹配和预加重。 动态输出缓冲电路包括控制电路（410）和输出电路（420）。 控制电路（410）包括预加重电路，阻抗匹配电路和寄存器电路。 控制电路（410）将金属线的特性阻抗与动态输出电路的输出阻抗相匹配。 输出电路（420）包括动态ODT（430）和输入级（440）。 输出电路（420）输出控制输出阻抗的至少一个输出信号（D / O），并对至少一个输入信号（D / I）进行预加重。

公开(公告)号：KR1020070060823A

公开(公告)日：2007-06-13

申请号：KR1020050120882

申请日：2005-12-09

Applicant: 삼성전자주식회사

Inventor： 이재준 ,  최주선 ,  김규현

IPC: G11C7/00 ,  G11C7/10

Abstract: A memory system and a signal transmitting/receiving method thereof are provided to enable high speed signal transmission by minimizing delay during signal transmission by reducing line loading of signal transmission lines. In a memory system comprising a memory control part(100), first memory modules(200-1) and second memory modules(200-2) transmit/receive data to/from the memory control part. Each memory module includes a first memory and a second memory, and the first memory outputs a control signal applied from the memory control part to the second memory, and the second memory receives read data output from the first memory and then outputs the read data to the memory control part. The control signal output from the memory control part is transmitted to the first memory of the first and the second memory modules in common through a control signal line, and the read data output from the second memory of the first memory module is transmitted to the memory control part through a first read data line, and the read data output from the second memory of the second memory module is transmitted to the memory control part through a second read data line.

Abstract translation: 提供了一种存储器系统及其信号发送/接收方法，以通过减少信号传输线路的线路负载来最小化信号传输期间的延迟来实现高速信号传输。 在包括存储器控制部分（100）的存储器系统中，第一存储器模块（200-1）和第二存储器模块（200-2）向/从存储器控制部分发送/接收数据。 每个存储器模块包括第一存储器和第二存储器，并且第一存储器将从存储器控制部分施加的控制信号输出到第二存储器，并且第二存储器接收从第一存储器输出的读取数据，然后将读取的数据输出到 存储器控制部分。 从存储器控制部输出的控制信号通过控制信号线被共同地发送到第一和第二存储器模块的第一存储器，并且从第一存储器模块的第二存储器输出的读取数据被发送到存储器 控制部分通过第一读取数据线，并且从第二存储器模块的第二存储器输出的读取数据通过第二读取数据线被发送到存储器控制部分。

公开(公告)号：KR1020070030056A

公开(公告)日：2007-03-15

申请号：KR1020050084813

申请日：2005-09-12

Applicant: 삼성전자주식회사

Inventor： 최주선

IPC: G06F12/00 ,  G11C7/10

Abstract: A semiconductor memory module and a semiconductor memory system are provided to largely increase data throughput and concurrency by making a host exchange a command, an address and/or data with a primary memory, and input/output the needed data through other idle ports of a secondary memory through a background operation at the same time. At least one primary memory(310) transceives the first packet data with the host(350) through the first port and transceives the second packet data with the host through the second port. At least one secondary memory(320) receives the second packet data from the primary memory through the third port. The secondary memory is connected to the matched primary memory in a point-to-point connection type. In case that the host performs a write operation to the secondary memory, the primary memory receives command, address and write data packet data from the host through the first port and relays the received packet data to the secondary memory through the second port.

Abstract translation: 提供半导体存储器模块和半导体存储器系统以通过使主机与初级存储器交换命令，地址和/或数据来大量增加数据吞吐量和并发性，并且通过其他空闲端口输入/输出所需数据 辅助内存通过后台操作同时进行。 至少一个主存储器（310）通过第一端口与主机（350）收发第一分组数据，并通过第二端口与主机收发第二分组数据。 至少一个辅助存储器（320）通过第三端口从主存储器接收第二分组数据。 次要存储器以点对点连接类型连接到匹配的主存储器。 在主机对辅助存储器执行写入操作的情况下，主存储器通过第一端口从主机接收命令，地址和写入数据分组数据，并通过第二端口将接收的分组数据中继到辅助存储器。