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公开(公告)号：KR100603721B1
公开(公告)日：2006-07-24
申请号：KR1020050050107
申请日：2005-06-11
Applicant: 재단법인서울대학교산학협력재단 , 삼성전자주식회사
IPC: H01L21/336
Abstract: 본 발명은 SOI 기판 상에 직렬 연결된 소자의 바디 바이어싱 구조에 관한 것으로, 공통 소스/드레인 영역의 정션 깊이를 얕게 만듦으로써, 통상적인 벌크 MOSFET처럼 하나의 바디 바이어싱 콘택만으로도 여러 개의 소자에 대해 바디 바이어싱을 가능하게 하여 SOI 기판의 플로팅 바디 효과(floating body effect)를 제거하는 효과가 있다.
SOI, 바디, 바이어스, 플로팅Abstract translation: 本发明涉及在SOI衬底上串联连接的元件的体偏置结构，并且通过使公共源极/漏极区域的结深度浅，可以提供一种体 从而实现偏置并消除SOI衬底的浮体效应。
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公开(公告)号：KR102248835B1
公开(公告)日：2021-05-10
申请号：KR1020140130236
申请日：2014-09-29
Applicant: 삼성전자주식회사
Abstract: 본발명에따른제 1 및제 2 비트라인에각각연결되는제 1 및제 2 페이지버퍼를포함하는불 휘발성메모리장치의동작방법은: 상기제 1 페이지버퍼의제 1 래치에저장된데이터에따라상기제 1 페이지버퍼의제 1 및제 2 래치노드를제 1 레벨로바이어스하는단계; 상기제 1 래치노드와인접한, 상기제 2 페이지버퍼의센싱노드를프리차지하는단계; 그리고상기센싱노드를프리차지하는동안상기제 1 래치에저장된데이터를상기제 1 페이지버퍼의제 2 래치로덤핑하는단계를포함하되, 상기센싱노드의프리차지동작이완료된후에도, 상기제 1 래치노드는상기제 1 레벨로유지되도록제어된다.
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公开(公告)号：KR102235492B1
公开(公告)日：2021-04-05
申请号：KR1020140110864
申请日：2014-08-25
Applicant: 삼성전자주식회사
Abstract: 본발명의실시예에따른복수의메모리셀들을프로그램하는불휘발성메모리장치의프로그램검증방법은복수의검증전압들을인가하는단계; 및상기복수의검증전압들중 하나의검증전압을기반으로상기복수의메모리셀들중 서로다른목표문턱전압산포범위들을각각갖는메모리셀들의프로그램완료여부를판별하는단계를포함한다.
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Patent Agency Ranking
公开(公告)号：KR1020140065185A
公开(公告)日：2014-05-29
申请号：KR1020120132420
申请日：2012-11-21
Applicant: 삼성전자주식회사
CPC classification number: G11C16/08 , G11C7/04 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/26
Abstract: The present invention relates to a semiconductor memory device which applies a temperature-compensated word line voltage to a word line in a data reading operation. In the present invention, disclosed is the semiconductor memory device comprising a memory cell array which includes a plurality of word lines, a plurality of bit lines, and a plurality of nonvolatile memory cells which are connected to the word lines and the bit lines; and a word line voltage applying unit which applies a temperature-compensated read voltage to a selected word line and applies a temperature-compensated pass voltage to an unselected word line in the reading operation.
Abstract translation: 半导体存储器技术领域本发明涉及在数据读取操作中将温度补偿字线电压施加到字线的半导体存储器件。 在本发明中，公开了包括存储单元阵列的半导体存储器件，该存储单元阵列包括连接到字线和位线的多个字线，多个位线和多个非易失性存储器单元; 以及字线电压施加单元，其对所选择的字线施加温度补偿读取电压，并且在读取操作中将温度补偿通过电压施加到未选择的字线。
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公开(公告)号：KR1020140055738A
公开(公告)日：2014-05-09
申请号：KR1020120122985
申请日：2012-11-01
Applicant: 삼성전자주식회사
CPC classification number: G11C16/3445 , G11C11/5635 , G11C16/0483 , G11C16/3436 , G11C16/344
Abstract: A non-volatile memory device according to an embodiment of the present invention comprises: a memory cell array including word lines and bit lines; and a control logic which performs a program operation to program memory cells connected to a selected word line by applying a program voltage to the selected word line of the memory cell array, and performs a delete operation to delete the memory cells by applying a delete voltage and a delete verify voltage to the selected word line, wherein the control logic extracts information of the deleted state of the memory cell by applying a read voltage to the selected word line, and controls the level of the delete verify voltage based on the delete state information.
Abstract translation: 根据本发明实施例的非易失性存储器件包括：包括字线和位线的存储单元阵列; 以及控制逻辑，其通过对存储单元阵列的所选择的字线施加编程电压来执行编程连接到所选字线的存储器单元的编程操作，并且通过施加删除电压来执行删除操作以删除存储器单元 以及对所选择的字线的删除验证电压，其中，所述控制逻辑通过对所选择的字线施加读取电压来提取所述存储器单元的删除状态的信息，并且基于所述删除状态来控制所述删除验证电压的电平 信息。
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公开(公告)号：KR1020130142421A
公开(公告)日：2013-12-30
申请号：KR1020120065626
申请日：2012-06-19
Applicant: 삼성전자주식회사
IPC: G11C16/06
CPC classification number: G11C16/3418 , G11C11/5628 , G11C16/06 , G11C16/10 , G11C16/26
Abstract: A nonvolatile memory device is provided. The nonvolatile memory device includes a nonvolatile memory chip which includes a static latch and a dynamic latch which receives data from the static latch through a floating node, a device controller which controls the operation of the nonvolatile memory chip, and a refresh controller which controls the refresh operation of the dynamic latch. The dynamic latch includes a storage node, a writing transistor which writes the data of the floating node on the storage node and a reading transistor which reads the data of the storage node. The writing transistor and the reading transistor share the floating node.
Abstract translation: 提供非易失性存储器件。 非易失性存储器件包括非易失性存储器芯片，其包括静态锁存器和通过浮动节点从静态锁存器接收数据的动态锁存器，控制非易失性存储器芯片的操作的器件控制器和控制非易失性存储器芯片的刷新控制器 动态锁存器的刷新操作。 动态锁存器包括存储节点，将浮动节点的数据写入存储节点的写入晶体管和读取存储节点的数据的读取晶体管。 写入晶体管和读取晶体管共享浮动节点。
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公开(公告)号：KR1020130099496A
公开(公告)日：2013-09-06
申请号：KR1020120021059
申请日：2012-02-29
Applicant: 삼성전자주식회사
CPC classification number: G11C7/04 , G11C16/0483 , G11C16/10
Abstract: PURPOSE: A non-volatile memory device and a memory system including the same reduce erasure disturbance by varying a program pulse period according to temperature change, the physical position of a word line, a program voltage, and/or a program-erasure cycle. CONSTITUTION: A program voltage (Vpgm) is supplied to a selected word line (Selected WL). A pass voltage is supplied to unselected word lines (Unselected WL). A program pulse period where the program voltage is constantly maintained is controlled by temperature change. The program pulse period is increased when the temperature is decreased, and the program pulse period is decreased when the temperature is increased. The program pulse period determined by the temperature change is additionally changed by the physical position of the selected word line.
Abstract translation: 目的：通过根据温度变化，字线的物理位置，程序电压和/或程序擦除循环改变编程脉冲周期来减少擦除干扰的非易失性存储器件和存储器系统。 构成：将程序电压（Vpgm）提供给选定的字线（选定的WL）。 向未选择的字线（未选择WL）提供通过电压。 通过温度变化来控制编程电压不断维持的编程脉冲期间。 当温度降低时，编程脉冲周期增加，并且当温度升高时编程脉冲周期减小。 由温度变化确定的编程脉冲周期由所选字线的物理位置附加地改变。
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公开(公告)号：KR1020130099495A
公开(公告)日：2013-09-06
申请号：KR1020120021058
申请日：2012-02-29
Applicant: 삼성전자주식회사
CPC classification number: G11C16/3459 , G11C11/5628 , G11C16/10 , G11C2211/5621
Abstract: PURPOSE: A non-volatile memory device and a memory system including the same improve the distribution of a threshold voltage by biasing a bulk to a negative voltage during a programming operation and/or a verification operation. CONSTITUTION: A program execution period is performed to supply a program voltage to a selected word line. A verification period is performed to supply a verification voltage to the selected word line. A negative voltage as a well bias voltage (Vbb) is supplied to a pocket well in which memory cells are formed during the verification period. The negative voltage or a ground voltage as the well bias voltage is supplied to the pocket well during the program execution period.
Abstract translation: 目的：非易失性存储器件和包括其的存储器系统在编程操作和/或验证操作期间通过将体积偏压到负电压来改善阈值电压的分布。 构成：执行程序执行周期以将编程电压提供给所选择的字线。 执行验证周期以向所选择的字线提供验证电压。 作为阱偏置电压（Vbb）的负电压被提供到在验证期间形成存储器单元的口袋中。 在程序执行期间，阱电压被提供给口袋中的负电压或接地电压。
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