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公开(公告)号：KR1020090027561A
公开(公告)日：2009-03-17
申请号：KR1020080047092
申请日：2008-05-21
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
IPC: G11C17/00 , H01L21/8239 , H01L23/12
Abstract: A multi-layered memory apparatus is provided to improve a data storage density by forming one or more memory layer by a plurality of sub arrays. A multi-layered memory apparatus includes two or more memory parts(12) and an active circuit part(11). The active circuit part includes a decoder, and is formed between the memory parts. The memory part includes one or more memory layer. The memory layer is a memory array of a cross point type, and has a plurality of sub arrays. The active circuit part is formed on a non-silicone substrate. The non-silicone substrate is made of plastic, glass, ceramic, oxide material, or nitride material.
Abstract translation: 提供一种多层存储装置，通过由多个子阵列形成一个或多个存储层来提高数据存储密度。 多层存储装置包括两个或多个存储器部件（12）和有源电路部件（11）。 有源电路部分包括解码器，并且形成在存储器部分之间。 存储器部分包括一个或多个存储器层。 存储层是交叉点类型的存储器阵列，并且具有多个子阵列。 有源电路部分形成在非硅衬底上。 非硅树脂基材由塑料，玻璃，陶瓷，氧化物材料或氮化物材料制成。
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公开(公告)号：KR101686582B1
公开(公告)日：2016-12-15
申请号：KR1020090129136
申请日：2009-12-22
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
IPC: H01L23/538
CPC classification number: H01L2924/0002 , H01L2924/00
Abstract: 유도결합통신수단을구비한전자소자가개시된다. 개시된유도결합통신수단을구비한전자소자는순차적으로적층된제1실리콘칩및 제2실리콘칩와, 상기제1실리콘칩상의제1인덕터및 상기제2실리콘칩상에서상기제1인덕터와대응되게배치되어상기제1인덕터와유도결합하는제2인덕터와, 상기제2실리콘칩에형성된관통홀;을구비한다. 기관통홀은상기제1인덕터에대응되게형성된다.
Abstract translation: 目的：提供一种包括电感耦合通信单元的电子设备，通过减少涡流来稳定地发送和接收具有低功率的信号。 构成：依次层叠第一硅芯片和第二硅芯片。 第一电感器（112）布置在第一硅芯片上。 第二电感器（122）布置在第二硅芯片上以对应于第一电感器并且与第一电感器感应耦合。 穿孔（130）形成在第二硅芯片上，并包括与第一电感相对应的电感耦合通信单元。 穿透孔形成在第二电感器中。 绝缘体填充穿透孔。
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公开(公告)号：KR101470520B1
公开(公告)日：2014-12-08
申请号：KR1020130015046
申请日：2013-02-12
Applicant: 성균관대학교산학협력단
Inventor： 권기원
Abstract: 본발명의반도체메모리장치는복수의저항성메모리셀을포함하는메모리셀 어레이및 1회액세스되는데이터에대해독출감도를가변시키면서상기복수의저항성메모리셀의저항값상태를판별하도록제어하는제어블록을포함한다. 따라서, 독출감도를가변시켜가며데이터의독출을수행함으로써전력소모및 동작시간의오버헤드를최소화할수 있고, 산포를극복하여신뢰성높은데이터독출을가능케한다.
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公开(公告)号：KR1020140101638A
公开(公告)日：2014-08-20
申请号：KR1020130015046
申请日：2013-02-12
Applicant: 성균관대학교산학협력단
Inventor： 권기원
CPC classification number: G11C13/004 , G11C7/1051 , G11C13/0004 , G11C16/26
Abstract: A semiconductor memory device according to the present invention includes a memory cell array which includes a plurality of resistive memory cells and a control block to determine the resistance state of the resistive memory cells while varying the reading sensitivity of data which is accessed once. Therefore, power consumption and overhead of operation time are minimized by reading the data while varying the reading sensitivity. The data with high reliability is read by overcoming a distribution.
Abstract translation: 根据本发明的半导体存储器件包括存储单元阵列，该存储单元阵列包括多个电阻存储器单元和用于确定电阻存储单元的电阻状态同时改变一次访问的数据的读取灵敏度的控制块。 因此，通过在改变读取灵敏度的同时读取数据来最小化功耗和操作时间的开销。 通过克服分布来读取具有高可靠性的数据。
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公开(公告)号：KR1020140084450A
公开(公告)日：2014-07-07
申请号：KR1020120153450
申请日：2012-12-26
Applicant: 성균관대학교산학협력단
CPC classification number: G11C13/0064 , G11C13/004 , G11C29/50008 , G11C2013/0054 , G11C2029/0409 , G11C13/00
Abstract: In the present invention, disclosed is a semiconductor memory device, and verification reading method and system. The semiconductor memory device includes a memory cell array including multiple resistant memory cells and a control block controlling to determine a resistant value state of the resistant memory cells based on a digital code value of at least 2 bits reflecting the resistant value state of the resistant memory cells. Therefore, as data of memory is distinguished by analyzing the distribution of digital code values, features of the current memory call array can be monitored and reliable data can be read.
Abstract translation: 在本发明中，公开了一种半导体存储器件，以及验证读取方法和系统。 半导体存储器件包括存储单元阵列，该存储单元阵列包括多个电阻存储器单元，以及一个控制块，用于基于至少2位的数字码值来确定电阻存储器单元的电阻值状态，反映电阻值存储器的电阻值状态 细胞。 因此，通过分析数字代码值的分布来区分存储器的数据，可以监视当前存储器调用阵列的特征并且可以读取可靠的数据。
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Patent Agency Ranking
公开(公告)号：KR101385637B1
公开(公告)日：2014-04-24
申请号：KR1020120122369
申请日：2012-10-31
Applicant: 성균관대학교산학협력단
CPC classification number: G11C13/0069 , G11C13/0064
Abstract: Disclosed are a semiconductor memory apparatus, a program method and a program system. The semiconductor memory apparatus comprises: a memory cell array including a plurality of resistive memory cells; and a control block configured to control at least one of an initial voltage magnitude and an initial voltage applying time to be variable during an incremental step pulse programming (ISPP) mode for the memory cells based on digital code values reflecting resistance states of the resistive memory cells. Therefore, even in the case of the worst cell, since an incremental step of the ISPP may be minimized, writing time may be reduced, and further, unnecessary current consumption may be reduced. [Reference numerals] (20) Row decoder; (30) Column decoding unit; (32) ADC unit; (34) Column decoder; (40) Reading/writing circuit; (50) Interface; (70) DC generator; (AA) Row address (RA); (BB) Column address (CA)
Abstract translation: 公开了一种半导体存储装置，程序方法和程序系统。 半导体存储装置包括：包括多个电阻存储单元的存储单元阵列; 以及控制块，被配置为基于反映所述电阻性存储器的电阻状态的数字代码值来控制所述存储器单元的增量步进脉冲编程（ISPP）模式期间的初始电压幅度和初始电压施加时间中的至少一个可变化 细胞。 因此，即使在最差小区的情况下，由于可以使ISPP的增量步长最小化，因此可以减少写入时间，进一步减少不必要的电流消耗。 （20）行译码器; （30）列解码单元; （32）ADC单元; （34）列解码器; （40）读/写电路; （50）接口; （70）直流发电机; （AA）行地址（RA）; （BB）列地址（CA）
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公开(公告)号：KR101232287B1
公开(公告)日：2013-02-12
申请号：KR1020110067281
申请日：2011-07-07
Applicant: 성균관대학교산학협력단
Inventor： 권기원
Abstract: 본 발명은 반도체 웨이퍼 또는 칩 등의 반도체소자들을 입체적으로 정렬할 때 반도체소자간 정렬을 위한 정렬장치에 관한 것이다. 본 발명에 따른 정렬장치는 제1반도체소자에 형성되며 소정 전기신호를 송신하는 송신 회로패턴; 상기 제1반도체소자의 상부 또는 하부에 위치하는 제2반도체소자에 형성되며 상기 송신 회로패턴에서 발신된 신호를 수신하는 수신 회로패턴; 및 상기 수신 회로패턴에서 수신된 신호의 세기 또는 강도를 감지하여 제1반도체소자와 제2반도체소자의 정렬 위치를 결정하는 위치결정부를 포함하여 구성된다. 본 발명에 따르면, 반도체소자들을 접합할 때 수신 회로패턴에서의 신호의 세기 또는 강도를 이용하여 반도체소자들을 정렬함으로써, 픽앤플레이스툴 등과 같은 재치장치에 의하여 반도체소자에 형성된 얼라인 마크나 패턴 등이 가려진 상태에서도 반도체소자간 정렬을 정확하게 할 수 있으며, 정렬오차에 의한 불량품 발생률을 현저하게 감소시키는 효과가 있다.
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公开(公告)号：KR1020120137204A
公开(公告)日：2012-12-20
申请号：KR1020110115363
申请日：2011-11-07
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
CPC classification number: H04B5/0075 , H01F38/14 , H03K17/56 , H03K19/018507
Abstract: PURPOSE: A semiconductor device is provided to reduce bit error ratio when using an inductive coupling method which uses an inductor with a coil between chips. CONSTITUTION: A transmission circuit(100) receives data and a clock signal. The transmission circuit is connected to a first coil. The transmission circuit flows a current through a first coil in response to the clock signal. A second coil(L2) is coupled with the first coil. A receiving circuit(200) is connected to the second coil. The receiving circuit receives the data from an induced voltage induced to the second coil. [Reference numerals] (100) Transmission circuit; (12) Output circuit; (14) Serialization circuit; (16,26) Reference clock generator; (18,28) Pulse generator; (200) Receiving circuit; (22) Input circuit; (24) Paralleling circuit
Abstract translation: 目的：提供一种半导体器件，以在使用电感耦合方法时减少误码率，该电感耦合方法在芯片之间使用线圈。 构成：发送电路（100）接收数据和时钟信号。 传输电路连接到第一线圈。 传输电路响应于时钟信号流过第一线圈的电流。 第二线圈（L2）与第一线圈耦合。 接收电路（200）连接到第二线圈。 接收电路从感应到第二线圈的感应电压接收数据。 （附图标记）（100）传输电路; （12）输出电路; （14）序列化电路; （16,26）参考时钟发生器; （18,28）脉冲发生器; （200）接收电路; （22）输入电路; （24）并联电路
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公开(公告)号：KR1020100061290A
公开(公告)日：2010-06-07
申请号：KR1020090038461
申请日：2009-04-30
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
IPC: H01L29/786
CPC classification number: H01L27/1225 , H01L27/092 , H01L27/1251
Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to improve a performance characteristic of the device by reducing a resistance with forming a p+ domain on the central part of a first oxide channel layer. CONSTITUTION: A first oxide channel layer(C10) is formed into a first conductive type oxide on a lower part layer. A first electrode layer covering the first channel layer is formed on the lower part layer. The first electrode layer and a second electrode layer separated are formed. A second oxide channel layer(C20) is formed into a second conductive type oxide on the lower part later. The first electrode layer is patterned. A first source, a first drain and the second drain are formed by the patterning of the first electrode layer.
Abstract translation: 目的：提供半导体器件及其制造方法，以通过在第一氧化物沟道层的中心部分形成p +畴来降低电阻来提高器件的性能特性。 构成：第一氧化物沟道层（C10）在下部层上形成为第一导电型氧化物。 覆盖第一沟道层的第一电极层形成在下部层上。 形成分离的第一电极层和第二电极层。 第二氧化物沟道层（C20）稍后在下部形成第二导电型氧化物。 图案化第一电极层。 通过图案化第一电极层形成第一源极，第一漏极和第二漏极。
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公开(公告)号：KR1020100040580A
公开(公告)日：2010-04-20
申请号：KR1020080099778
申请日：2008-10-10
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
IPC: H01L21/8239
CPC classification number: G11C5/02 , G11C5/143 , G11C7/18 , G11C8/12 , G11C13/0023 , G11C2213/71
Abstract: PURPOSE: A stacked memory device is provided to reduce the area in which the stacked memory device is occupied by stacking active circuit parts between memory layers. CONSTITUTION: Stacked memory layers(110) include memory cell array. A first active circuit part(140) processes the address information of the memory cell array which is divided into vertical address information and horizontal address information. A second active circuit part(160) is arranged on the first active circuit part. The second active circuit part generates memory selection signal to each memory cell based on the processed signal of the first active circuit parts. The first active circuit part includes a level decoder(120) and a pre decoder(130). The level decoder decodes the vertical address information. The pre decoder decodes the horizontal address information.
Abstract translation: 目的：提供堆叠的存储器件，以通过在存储器层之间堆叠有源电路部分来减少堆叠的存储器件被占用的区域。 构成：堆叠的存储器层（110）包括存储单元阵列。 第一有源电路部分（140）处理被划分为垂直地址信息和水平地址信息的存储单元阵列的地址信息。 第二有源电路部分（160）布置在第一有源电路部分上。 第二有源电路部分基于第一有源电路部分的处理信号，向每个存储器单元产生存储器选择信号。 第一有源电路部分包括电平解码器（120）和预解码器（130）。 电平解码器解码垂直地址信息。 预解码器解码水平地址信息。
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