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公开(公告)号：KR1019940000149B1
公开(公告)日：1994-01-07
申请号：KR1019900018074
申请日：1990-11-09
Applicant: 한국전자통신연구원
IPC: G11C11/409
Abstract: The device includes three NMOS transistors (MN1,MN2,MN3) and two PMOS transistors (MP6,MP7), a 1st amplifying means for amplifying the difference voltage of a nodes (1)(2) by the 1st sensing signal (PSN1) of the low edge, a 2nd amplifying means for amplifying the difference voltage of the two nodes(1)(2) by the 2nd sensing signal (PSP1) of the low edge, a 3rd amplifying means for amplifying the difference voltage of two nodes (4)(5) by the 3rd sensing signal (PSN2) of the low edge, a 4th amplifying means for amplifying the difference voltage of the two nodes(4)(5) by the 4th sensing signal (PSP2) of the low edge, This method improves the sensitivity of the differential amplifier and, the sensing speed is within the 3nd.
Abstract translation: 该装置包括三个NMOS晶体管（MN1，MN2，MN3）和两个PMOS晶体管（MP6，MP7），第一放大装置，用于通过第一感测信号（PSN1）放大节点（1）（2）的差分电压 低边缘，用于通过低边缘的第二感测信号（PSP1）放大两个节点（1）（2）的差分电压的第二放大装置，用于放大两个节点（4）的差分电压的第三放大装置 ）（5）通过低边缘的第三感测信号（PSN2），第四放大装置，用于通过低边缘的第四感测信号（PSP2）放大两个节点（4）（5）的差分电压。 方法提高了差分放大器的灵敏度，感测速度在3号以内。
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公开(公告)号：KR1019930022587A
公开(公告)日：1993-11-24
申请号：KR1019920006119
申请日：1992-04-13
Applicant: 한국전자통신연구원
IPC: H01L29/76
Abstract: 본 발명은 딥서브 미크론(deep sumicron)급 MOSFET장치의 제조 방법에 관한 것으로, 그 제조방법을 웰을 형성하고 격리(isolation) 시킨다음, 게이트산화막을 증착하고 폴리실리콘 게이트를 형성하고, N층을 형성한 후 측벽스페이서를 형성하고, N
+ 이온주입을 한다음 펀치 쓰루 방지용 이온주입을 하여 자기정렬에 의한 다단구조로 형성하고, CVD산화막을 증착하고, 콘택을 뚫고 금속을 증착하여 패터닝(patterning)함으로써 딥서브 미크론급VLSI를 제조하는데 적합한 것이 특징이다.-
Patent Agency Ranking
公开(公告)号：KR1019930010985B1
公开(公告)日：1993-11-18
申请号：KR1019900021831
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: H01L21/70
Abstract: The isolation using various local poly oxides is prepared by: depositing 10-100 nm thick oxide film (12) on a substrate (11); depositing 50-200 nm thick 1st polysilicon layer (13); depositing 100-200 m thick nitride film (14); forming a photosensitive film (15); forming nitride film pattern by photoresist process; implanting channel-stopping impurities (IE13-IE15), depositing and oxidizing 2nd polysilicon film (16) to form poly oxide film (17); etch-backing the poly oxide film to the part of nitride film (14); removing the nitride film (14) and 1st polysilicon oxide film (12) in order to form oxide (19) for device isolation.
Abstract translation: 使用各种局部多氧化物的隔离是通过：在衬底（11）上沉积10-100nm厚的氧化膜（12）; 沉积50-200nm厚的第一多晶硅层（13）; 沉积100-200μm厚的氮化物膜（14）; 形成感光膜（15）; 通过光刻胶工艺形成氮化物膜图案; 注入通道停止杂质（IE13-IE15），沉积和氧化第二多晶硅膜（16）以形成多晶氧化膜（17）; 将多晶氧化物膜蚀刻到氮化物膜（14）的一部分上; 去除氮化物膜（14）和第一多晶硅氧化膜（12）以形成用于器件隔离的氧化物（19）。
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公开(公告)号：KR1019930008579B1
公开(公告)日：1993-09-09
申请号：KR1019900004604
申请日：1990-04-03
Applicant: 한국전자통신연구원
IPC: H01L27/108
Abstract: The method for increasing the capacitor surface comprises steps: (a) forming a transistor on a silicon substrate; (b) forming a polycide layer, depositing a LTO, etching the defined bit line region, and forming an oxide layer spacer to form a bit line; (c) forming a storage electrode contact region by forming a silicon nitride, and a 1st silicon oxide layers; (d) forming a 1st polysilicon, 2nd silicon oxide, a 2nd polysilicon, and a 3rd silicon oxide layers in sequence; (e) etching them after defining the column type isolation region; (f) connecting a 1st and 2nd polysilicon with the polysilicon spacer; (g) forming the storage electrode by removing the 1st and 3rd silicon oxide layers; and (h) forming the plate electrode by forming the capacitor dielectric layer to ONO structure.
Abstract translation: 增加电容器表面的方法包括以下步骤：（a）在硅衬底上形成晶体管; （b）形成多晶硅化物层，沉积LTO，蚀刻所定义的位线区域，以及形成氧化物层间隔物以形成位线; （c）通过形成氮化硅和第一氧化硅层形成存储电极接触区; （d）依次形成第一多晶硅，第二氧化硅，第二多晶硅和第三氧化硅层; （e）在定义柱型隔离区之后蚀刻它们; （f）将第一和第二多晶硅与多晶硅间隔物连接; （g）通过去除第一和第三氧化硅层形成存储电极; 和（h）通过将电容器介电层形成ONO结构来形成平板电极。
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公开(公告)号：KR1020150072495A
公开(公告)日：2015-06-30
申请号：KR1020130159252
申请日：2013-12-19
Applicant: 한국전자통신연구원
Abstract: 본발명은고속정류동작을수행할수 있는정류소자에관한것으로서, 제1반도체층, 제2반도체층및 제3반도체층을포함하고, 상기제1반도체층및 제3반도체층은동일한타입의반도체층으로형성되며, 상기제2반도체층은상기제1반도체층및 상기제3반도체층사이에형성되고, 상기제1반도체층및 상기제3반도체층과는다른타입(Type)의반도체층으로형성되며, 경사도핑(Graded doping)된상태로형성되는것을특징으로한다.
Abstract translation: 本发明涉及能够执行高速整流操作的整流器。 整流器包括：第一半导体层，第二半导体层和第三半导体层。 第一半导体层的类型与第三半导体层的类型相同。 第二半导体层形成在第一半导体层和第三半导体层之间。 第二半导体层的类型与第一半导体层和第三半导体层的不同。 第二半导体层形成为渐变掺杂形式。
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公开(公告)号：KR1020140038869A
公开(公告)日：2014-03-31
申请号：KR1020130032972
申请日：2013-03-27
Applicant: 한국전자통신연구원
CPC classification number: G02F1/353 , G02F2203/13 , H01L31/02161 , H01L31/03046 , H01L31/14 , H01L31/1844
Abstract: Disclosed is a photomixer which basically solves a present lamination element in a photomixer and a PCA which is a core part of an existing broadband tera hertz spectroscopy. The photomixer includes an active layer which is formed on the upper surface of a substrate and formed in one region where light enters, and a thermal conductive layer which is formed on the upper surface of a substrate and is formed in the other region. The active layer has a mesa-type cross section. The thermal conductive layer has a flat surface by regrowing the other region with a MOCVD method.
Abstract translation: 公开了一种基本上解决了混合器中的本层叠元件的光敏混合器和作为现有宽带泰勒赫兹光谱的核心部分的PCA。 该混色器包括形成在基板的上表面并形成在一个光入射区域中的有源层和形成在基板的上表面上并形成在另一区域中的导热层。 有源层具有台面型横截面。 导热层通过用MOCVD方法重新生长另一区域而具有平坦的表面。
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