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公开(公告)号：DE60033529T2
公开(公告)日：2007-11-15
申请号：DE60033529
申请日：2000-08-24
Applicant: IBM
Inventor： BASS BRIAN , CALVIGNAC JEAN , HEDDES MARCO , PATEL PIYUSH , REVILLA JUAN , SIEGEL MICHAEL , VERPLANKEN FABRICE
IPC: G06F15/16 , G06F15/167 , G06F12/00 , G06F12/06 , G06F13/16 , G06F15/177 , H04L12/56 , H04Q11/04
Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate. The memory elements and interface processors together form a network processor capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by the plurality of processors.
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公开(公告)号：DE60205231T2
公开(公告)日：2006-05-24
申请号：DE60205231
申请日：2002-03-28
Applicant: ALCATEL SA , IBM
Inventor： BARRI PETER , CALVIGNAC JEAN , HEDDES MARCO , LOGAN JOSEPH , NIEMEGEERS ALEX , VERPLANKEN FABRICE , VRANA MIROSLAV
Abstract: A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.
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公开(公告)号：DE60015186T2
公开(公告)日：2006-02-02
申请号：DE60015186
申请日：2000-12-21
Applicant: IBM
Inventor： BASS MITCHELL , CALVIGNAC LOUIS , DAVIS TAYLOR , GALLO MATTEO , HEDDES MARCO , JENKINS KENNETH , LEAVENS BOYD , SIEGEL STEVEN , VERPLANKEN JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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公开(公告)号：CA2385339C
公开(公告)日：2005-06-28
申请号：CA2385339
申请日：2000-12-21
Applicant: IBM
Inventor： JENKINS STEVEN KENNETH , SIEGEL MICHAEL STEVEN , CALVIGNAC JEAN LOUIS , BASS BRIAN MITCHELL , LEAVENS ROSS BOYD , VERPLANKEN FABRICE JEAN , HEDDES MARCO , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristic s for the frame (or input information unit) include the type of layer 3 protoc ol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics o f the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction addre ss and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed a nd forwarded in the same order in which they are received.
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公开(公告)号：DE60015186D1
公开(公告)日：2004-11-25
申请号：DE60015186
申请日：2000-12-21
Applicant: IBM
Inventor： BASS MITCHELL , CALVIGNAC LOUIS , DAVIS TAYLOR , GALLO MATTEO , HEDDES MARCO , JENKINS KENNETH , LEAVENS BOYD , SIEGEL STEVEN , VERPLANKEN JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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Patent Agency Ranking
公开(公告)号：PL363474A1
公开(公告)日：2004-11-15
申请号：PL36347402
申请日：2002-02-20
Applicant: IBM
Inventor： CALVIGNAC JEAN LOUIS , HEDDES MARCO , LOGAN JOSEPH FRANKLIN , VERPLANKEN FABRICE JEAN
IPC: H04L12/861 , H04L12/00
Abstract: A method and system for reducing the number of accesses to memory to obtain the desired field information in frame control blocks. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data, where each frame of data may have an associated frame control block. Each frame control block comprises a first and a second control block. The processor may further comprise a first memory coupled to the data flow unit configured to store field information for the first control block. The processor may further comprise a scheduler coupled to the data flow unit where the scheduler is configured to schedule frames of data received by data flow unit. The scheduler may comprise a second memory configured to store field information for the second control block.
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公开(公告)号：AU2002242874A1
公开(公告)日：2002-10-21
申请号：AU2002242874
申请日：2002-03-28
Applicant: IBM
Inventor： VRANA MIROSLAV , CALVIGNAC JEAN , VERPLANKEN FABRICE , BARRI PETER , LOGAN JOSEPH , HEDDES MARCO , NIEMEGEERS ALEX
Abstract: A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.
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公开(公告)号：AU9012901A
公开(公告)日：2002-04-08
申请号：AU9012901
申请日：2001-09-27
Applicant: IBM
Inventor： HEDDES MARCO
Abstract: A timer management system and method for managing timers in both a synchronous and asynchronous system. In one embodiment of the present invention, a timer management system comprises an application program interface (API) for providing a set of synchronous functions allowing an application to functionally operate on the timer. The timer management system further comprises a timer database for storing timer-related information. Furthermore, the timer management system comprises a timer services for detecting the expiring of the timer. A handle function of the timer services allows an asynchronous application, i.e., application in a multi-task system, to synchronously act on the timer. That is, when a timer in a asynchronous system times-out, the handle function allows the asynchronous application to act on the expired timer without incurring an illegal time-out message. In another embodiment of the present invention, a timer may be reinitialized from the same allocated block of memory used to create the timer. In another embodiment of the present invention, a time-out message may be sent using the same allocated block of memory used to create the timer.
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公开(公告)号：AU4441801A
公开(公告)日：2001-10-23
申请号：AU4441801
申请日：2001-04-10
Applicant: IBM
Inventor： GALLO ANTHONY MATTEO , HEDDES MARCO , HARIHARAN SEETA , RAO SRIDHAR , ROVER SONIA KIANG
Abstract: A system and method for controlling overall behavior of a network processor device implemented in a network processing environment servicing a communications network. The method includes steps of receiving a guided control frame including one or more control functions for configuring various functional devices within the network processor with device control parameter data; a step of forwarding one or more control functions from a received control frame to a functional device within the network processor to be configured; and, executing the control functions as specified in the control frame. A novel control frame data structure and communications infrastructure is implemented whereby any network processor device operating in a distributed network processing environment may be controlled in accordance with executed control functions and device control parameter data.
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公开(公告)号：CA2385339A1
公开(公告)日：2001-07-12
申请号：CA2385339
申请日：2000-12-21
Applicant: IBM
Inventor： HEDDES MARCO , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , GALLO ANTHONY MATTEO , DAVIS GORDON TAYLOR , BASS BRIAN MITCHELL , VERPLANKEN FABRICE JEAN , CALVIGNAC JEAN LOUIS , JENKINS STEVEN KENNETH
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristic s for the frame (or input information unit) include the type of layer 3 protoc ol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics o f the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction addre ss and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed a nd forwarded in the same order in which they are received.
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