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    FLASH MEMORY WITH SIDEWALL FLOATING GATE, AND MANUFACTURE THEREOF
    41.
    发明专利
    FLASH MEMORY WITH SIDEWALL FLOATING GATE, AND MANUFACTURE THEREOF 失效

    公开(公告)号：JP2000040756A

    公开(公告)日：2000-02-08

    申请号：JP16743599

    申请日：1999-06-14

    Applicant: IBM

    Inventor： LEWIS L SUU ,  MANDELMAN JACK A

    IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    Abstract: PROBLEM TO BE SOLVED: To design and manufacture a high density flash memory by few number of treatment processes by a method, wherein a polycrystalline silicon spacer is formed on the second side wall having the tilt angle larger than the first sidewall, in such a manner that one side of the polycrystalline silicon spacer is opposed to a word line. SOLUTION: A gate oxide film 3 is formed on a substrate 1, and a gate 4, consisting of n+ or p+ dopant doped polycrystalline silicon, is formed. Then, one sidewall (a second sidewall) 4B of the gate 4 is formed vertically, and the other sidewall (a first side wall) 4A is formed at a tilt angle 45 to 65 degrees. Then, a polycrystalline silicon layer is adhered over the entire surface of a nitride layer and an oxide layer, and the first spacer of polycrystalline silicon and the second spacer which is connected to the first spacer are formed on the part, adjacent to the second sidewall 4B by anisotropic etching in the direction vertical to the surface of the silicon substrate 1. The first and the second spacers are incorporated and function as a sidewall floating gate 7.

    METHOD FOR REDUCING STAND-BY CURRENT FOR DYNAMIC RANDOM ACCESS MEMORY
    42.
    发明专利
    METHOD FOR REDUCING STAND-BY CURRENT FOR DYNAMIC RANDOM ACCESS MEMORY 失效

    公开(公告)号：JPH11265574A

    公开(公告)日：1999-09-28

    申请号：JP37452498

    申请日：1998-12-28

    Applicant: SIEMENS AG ,  IBM

    Inventor： HOENIGSCHMID HEINZ ,  KLEINHENZ RICHARD L ,  MANDELMAN JACK A

    IPC: G11C11/408 ,  G11C5/14 ,  G11C11/403 ,  G11C11/4074

    Abstract: PROBLEM TO BE SOLVED: To make a standby operation mode in which a leakage current is reduced executable by obtaining whether a DRAM is in the standby operation mode or in a normal operation mode and turning a first power source with respect to the array of the DRAM off when the DRAM is in the standby operation mode and maintaing the first power source with respect to the array of the DRAM when it is in the normal operation mode. SOLUTION: A collar 268 is provided at the upward part of a trench in order to separate a p-well from a storage node, an n-well area or an n-band area exists at the downward direction of the p-weel and the embedding plate 265 of capacitances in these n areas is connected to the embedding plates of other DRAM cells of the array. The reducing of stand-by currents is achieved by switching off a voltage generator or a voltage pump supplying a proper voltage to the n-well during the stanby mode and the voltage pump for the n-band with respect to the array of the DRAM is kept as switched on.

    MEMORY CELL
    43.
    发明专利
    MEMORY CELL 失效

    公开(公告)号：JPH11168190A

    公开(公告)日：1999-06-22

    申请号：JP27728998

    申请日：1998-09-30

    Applicant: SIEMENS AG ,  IBM

    Inventor： MANDELMAN JACK A ,  HSU LOUIS L C ,  ALSMEIER JOHANN ,  TONTI WILLIAM R

    IPC: H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To obtain a small trench capacitor having sufficiently low parasitic leakage. SOLUTION: A transistor, which includes a gate and first and second diffused regions are provided. A trench capacitor in a substrate electrically connects a dielectric color part 168 at the upper-side part of a trench, a diffused region embedded in a substrate surrounding the lower part of the trench capacitor, a transitor and the capacitor. A node diffused region is included on a collar part. A third diffused region 269 is provided in a substrate neighboring the color part. In order to decrease the leakage, an adequate concentration of doping agent for enhancing the threshold voltage of the gate of a parasitic transistor, which is formed of the color part, the embedded diffused region and node diffusion, is provided.

    NEW BUILT-IN STRAP FOR TRENCH STORAGE CAPACITOR IN DRAM TRENCH CELL
    44.
    发明专利
    NEW BUILT-IN STRAP FOR TRENCH STORAGE CAPACITOR IN DRAM TRENCH CELL 失效

    公开(公告)号：JPH1131797A

    公开(公告)日：1999-02-02

    申请号：JP15505798

    申请日：1998-06-03

    Applicant: IBM

    Inventor： MARK C HEIKY ,  DAVID V HORAK ,  MANDELMAN JACK A ,  WENDEL P NOBLE

    IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To obtain a built-in strap structure which makes a device transfer gate longer in length by the use of a smaller cell region by a method wherein the inside of a storage trench is connected to the rear of an array transfer device, and the strap is arranged in a region which is used only for isolation. SOLUTION: An empty region inside a shallow trench isolation region 82 for a built-in strap which avoids a deep trench collar is used. The layout of a built-in strap indicated by an arrow 80 is carried out in a shallow trench isolation region 82. A space inside a transfer gate 84 between deep trenches 86 is not affected by the built-in strap. By this setup, a built-in strap structure which gives a longer device transfer gate length by the use of a smaller cell region can be obtained.

    METHOD OF MANUFACTURING SUBSTITUTE FOR DUAL GATE OXIDE OF MOSFET
    49.
    发明专利
    METHOD OF MANUFACTURING SUBSTITUTE FOR DUAL GATE OXIDE OF MOSFET 失效

    公开(公告)号：JP2001274262A

    公开(公告)日：2001-10-05

    申请号：JP2001044604

    申请日：2001-02-21

    Applicant: IBM

    Inventor： TONTI WILLIAM R ,  MANDELMAN JACK A

    IPC: H01L21/266 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  H01L27/11

    Abstract: PROBLEM TO BE SOLVED: To provide a MOSFET array where a high voltage device and a low voltage device are formed on the same substrate. SOLUTION: A method for forming a MOSFET array includes a step for preparing a substrate, a step for forming ac conductor layer on the substrate, a step for injecting dopant species into conductor layer, a step for counter- doping the non-mask part of the doped conductor layer and masking a part of the doped conductor layer and step for forming a depletion conductor region on the substrate. Thus, the substitute of dual gate oxide for MOSFET, in which a high voltage region in the counter-doped part is used for the memory array of DRAM, EDRAM, SRAM and NVRAM and the like, is supplied.

    VERTICAL SIDEWALL DEVICE ALIGNED TO CRYSTAL AXIS AND MANUFACTURE THEREOF
    50.
    发明专利
    VERTICAL SIDEWALL DEVICE ALIGNED TO CRYSTAL AXIS AND MANUFACTURE THEREOF 失效

    公开(公告)号：JP2001044390A

    公开(公告)日：2001-02-16

    申请号：JP2000209997

    申请日：2000-07-11

    Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

    Inventor： BRONNER GARY ,  GRUENING ULRIKE ,  MANDELMAN JACK A ,  RADENS CARL J

    IPC: H01L27/108 ,  H01L21/8242

    Abstract: PROBLEM TO BE SOLVED: To obtain non-planar type transistor structure by arranging an active transistor device partially on the sidewall of a deep trench in a cell, and aligning the side wall to a first crystal plane with a crystal orientation along the single- crystal axis. SOLUTION: A deep trench accumulation capacitor 10 is formed in a pad 22 and a substrate 24, and a pattern is formed on the pad 22 using a light lithography step. Then, using such a dry etching step as reactive ion etching, a trench 20 is formed to a desired depth in the substrate 24 through the pad 22. Then, an active transistor device is partially provided on a sidewall 32 of the trench 20, and the sidewall 32 is aligned to first crystal planes (001) and (011) with a crystal orientation set along the single-crystal axis.

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