公开(公告)号：JP2002230965A

公开(公告)日：2002-08-16

申请号：JP2001015475

申请日：2001-01-24

Applicant: IBM

Inventor： ASANO HIDEO ,  SUNANAGA TOSHIO ,  KITAMURA TSUNEJI ,  MIYATAKE HISATADA ,  UMEZAKI HIROSHI ,  NODA HIROYOSHI

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To improve the reliability of recording of a MRAM. SOLUTION: This device has read-out word lines WLR and write-in word lines WLW extending in the direction of (y), and write-in read-out bit lines BLW/R and write-in bit lines BLW extending in the direction of (x), and a memory cell MC is arranged at an intersection of a word line and a bit line. The memory cell MC comprises a sub-cell SC1 and a sub-cell SC2, the sub-cell SC1 comprises magnetic resistance elements MTJ1, MTJ2, and a selection transistor Tr1, and the sub-cell SC2 comprises magnetic resistance elements MTJ3, MTJ4, and a selection transistor Tr2, and the sub-cell SC2, The magnetic resistance elements MTJ1 and MTJ2 are connected in parallel, also, the magnetic resistance elements MTJ3 and MTJ2 are connected in parallel. The sub- cells SC1 and SC2 are connected in series between the write-in read-out bit lines BLW/R and ground.

公开(公告)号：JP2001144619A

公开(公告)日：2001-05-25

申请号：JP30208899

申请日：1999-10-25

Applicant: IBM

Inventor： MIYATAKE HISATADA

IPC: G06F9/48 ,  G06F7/74 ,  G06F9/46 ,  H03M1/36 ,  H03M7/00 ,  H03M7/14

Abstract: PROBLEM TO BE SOLVED: To provide a priority encoder that is miniaturized by decreasing its number of components and attains high-speed encoding. SOLUTION: The priority encoder 10 consists of means 12a, 12b, 12c, 12d detecting it that a true value input is given to at least one of input lines includes in each high-order bit dependent group with respect to the high-order bit dependent groups where high-order bits of output codes ('A3 A2 A1 A0') belong to the same input line, a means 20 that outputs a code ('A3 A2') of the high- order bits corresponding to the highest ranking high-order bit dependent group whose ranking is highest among the high-order bit dependent groups whose true value input is detected, means 22, 24, 26 that inactive the input given to the input line included in the high-order bit dependent group whose ranking is lower than the highest high-order bit dependent group, means 18a, 18b, 18c, 18d that detect the true value input to each low-order bit dependent group configured with the same input line for the low-order bits of the output code, and a means 40 that outputs a code ('A1 A0') of the low-order bit corresponding to the group whose ranking is highest among the low-order bit dependent groups whose true value input is detected.

公开(公告)号：JP2000228090A

公开(公告)日：2000-08-15

申请号：JP2831599

申请日：1999-02-05

Applicant: IBM

Inventor： MIYATAKE HISATADA ,  TANAKA MASAHIRO ,  MORI YOTARO

IPC: G11C8/08 ,  G11C7/12 ,  G11C15/00 ,  G11C15/04

Abstract: PROBLEM TO BE SOLVED: To reduce average power consumption in search operation of CAM without affecting performance of CAM. SOLUTION: Relating to each word accompanying bits (valid bit) indicating whether data of at the word is valid or not in CAM, a circuit is constituted so that when a valid bit indicates that the word is invalid, pre-charge is controlled so that pre-charge of a match line of the word is prohibited, and a match line is forcedly in a 'uncoincidence state'. Thereby, power consumption caused by search operation by a data word being not a search object is prevented, and power consumption of search operation of the whole CAM is reduced.

公开(公告)号：JPH08241963A

公开(公告)日：1996-09-17

申请号：JP2267895

申请日：1995-02-10

Applicant: IBM

Inventor： MIYATAKE HISATADA ,  SUNANAGA TOSHIO ,  KITAMURA TSUNEJI ,  YAMAMOTO MASAAKI

IPC: G11C11/401 ,  G11C5/14 ,  H01L21/8242 ,  H01L27/108

Abstract: PURPOSE: To provide a reliable high-density semiconductor integrated circuit device with high-speed operation by forming a DRAM macrocell and a logical cell in a common chip. CONSTITUTION: A DRAM macroscopic cell 14 is formed on the same cell as a logical cell. The DRAM macroscopic cell 14 includes a guard ring 26 of a conductive type opposite to that of a semiconductor substrate, a memory cell alley 42 formed in a well in the guard ring 26, a power line 34, a grounding line 36, and a bypass capacitor 70 joined between the power line 34 and the grounding line 36. The power line 36 and a logical-cell power line are connected to different power pads, while the grounding line 36 and a logic-cell grounding line are connected to a common grounding line or to grounding lines provided near to each other and connected with a low impedance line.