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公开(公告)号：GB2500553A
公开(公告)日：2013-09-25
申请号：GB201313026
申请日：2011-12-19
Applicant: IBM
Inventor： PORET MICHEL LOUIS RAYMOND , BASSO CLAUDE , CALVIGNAC JEAN L , CHANG CHIH-JEN , PHILIPPE DAMON , VAIDHYANATHAN NATARAJAN , VERRILLI COLIN , VERPLANKEN FABRICE JEAN
Abstract: The invention provides a method for adding specific hardware on both receive and transmit sides that will hide to the software most of the effort related to buffer and pointers management. At initialization, a set of pointers and buffers is provided by software, in quantity large enough to support expected traffic. A Send Queue Replenisher (SQR) and Receive Queue Replenisher (RQR) hide RQ and SQ management to software. RQR and SQR fully monitor pointers queues and perform recirculation of pointers from transmit side to receive side.
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公开(公告)号：DE60042162D1
公开(公告)日：2009-06-18
申请号：DE60042162
申请日：2000-08-24
Applicant: IBM
Inventor： ALLEN JAMES JR , BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , GAUR SANTOSH PRASAD , HEDDES MARCO C , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors and a suite of peripheral elements formed on a semiconductor substrate. The interface processors and peripherals together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.
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公开(公告)号：DE60132437T2
公开(公告)日：2009-01-08
申请号：DE60132437
申请日：2001-03-26
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , HEDDES MARCO , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a plurality of calendars with different service rates to allow a user to select the service rate which he desires. If a customer has chosen a high bandwidth for service, the customer will be included in a calendar which is serviced more often than if the customer has chosen a lower bandwidth.
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公开(公告)号：AT333678T
公开(公告)日：2006-08-15
申请号：AT00959158
申请日：2000-08-24
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , GALLO ANTHONY MATTEO , HEDDES MARCO C , PROPERTY LAW HURSLEY PARK , RAO SRIDHAR , SIEGEL MICHAEL STEVEN , YOUNGMAN BRIAN ALAN , VERPLANKEN FABRICE JEAN
IPC: G06F15/16 , G06F13/40 , G06F15/177 , H04L12/56 , G06F13/00 , G06F13/38 , G06F15/00 , G06F15/76 , G06F15/173
Abstract: An apparatus is disclosed for transporting control information in a communications system. The apparatus comprises a network processor, a control point processor operatively coupled to the network processor, and a guided frame generated by the control point processor. The guided frame comprises a first section in which frame control information is placed and is used by the network processor to update at least one control register within the network processor; a second section carrying correlators assigned by the control point processor to correlate guided frame responses with their requests; a third section carrying one or a sequence of guided commands; and an End delimiter guided command.
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公开(公告)号：CA2385339C
公开(公告)日：2005-06-28
申请号：CA2385339
申请日：2000-12-21
Applicant: IBM
Inventor： JENKINS STEVEN KENNETH , SIEGEL MICHAEL STEVEN , CALVIGNAC JEAN LOUIS , BASS BRIAN MITCHELL , LEAVENS ROSS BOYD , VERPLANKEN FABRICE JEAN , HEDDES MARCO , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristic s for the frame (or input information unit) include the type of layer 3 protoc ol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics o f the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction addre ss and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed a nd forwarded in the same order in which they are received.
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Patent Agency Ranking
公开(公告)号：PL363474A1
公开(公告)日：2004-11-15
申请号：PL36347402
申请日：2002-02-20
Applicant: IBM
Inventor： CALVIGNAC JEAN LOUIS , HEDDES MARCO , LOGAN JOSEPH FRANKLIN , VERPLANKEN FABRICE JEAN
IPC: H04L12/861 , H04L12/00
Abstract: A method and system for reducing the number of accesses to memory to obtain the desired field information in frame control blocks. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data, where each frame of data may have an associated frame control block. Each frame control block comprises a first and a second control block. The processor may further comprise a first memory coupled to the data flow unit configured to store field information for the first control block. The processor may further comprise a scheduler coupled to the data flow unit where the scheduler is configured to schedule frames of data received by data flow unit. The scheduler may comprise a second memory configured to store field information for the second control block.
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公开(公告)号：AU2002347376A1
公开(公告)日：2003-07-09
申请号：AU2002347376
申请日：2002-12-09
Applicant: IBM
Inventor： CALVIGNAC JEAN LOUIS , VERPLANKEN FABRICE JEAN
Abstract: A system includes a data structure having a Direct Table (DT), Patricia-Trees, Pointers and high speed storage systems such as Contents Address Memory (CAM). The DT has a plurality of entries with each one coupled to a Patricia Tree having multiple nodes coupled to leaves. The number of Nodes, termed a threshold, that can be traversed to obtain information in the leaves is limited to a predetermined value. Once the threshold is reached a pointer indicates the address of the CAM and the address of the leaves is stored in the CAM. By using the structure and method the latency associated with tree search is significantly reduced.
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公开(公告)号：CA2385339A1
公开(公告)日：2001-07-12
申请号：CA2385339
申请日：2000-12-21
Applicant: IBM
Inventor： HEDDES MARCO , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , GALLO ANTHONY MATTEO , DAVIS GORDON TAYLOR , BASS BRIAN MITCHELL , VERPLANKEN FABRICE JEAN , CALVIGNAC JEAN LOUIS , JENKINS STEVEN KENNETH
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristic s for the frame (or input information unit) include the type of layer 3 protoc ol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics o f the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction addre ss and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed a nd forwarded in the same order in which they are received.
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公开(公告)号：GB2502455A
公开(公告)日：2013-11-27
申请号：GB201312415
申请日：2011-12-12
Applicant: IBM
Inventor： VERPLANKEN FABRICE JEAN , CALVIGNAC JEAN , ABEL FRANCOIS , CHANG CHIH-JEN , PHILLIPE DAMON
Abstract: The invention provides for a network processor comprising a parser, the parser being operable to work in normal operation mode or in repeat operation mode, the parser in normal operation mode loading and executing at least one rule in a first and a second working cycle respectively, the parser in repeat operation mode being operable to repeatedly execute a repeat-instruction, the execution of each repeat corresponding to one working cycle.
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公开(公告)号：DE102013208212A1
公开(公告)日：2013-11-21
申请号：DE102013208212
申请日：2013-05-06
Applicant: IBM
Inventor： CALVIGNAC JEAN L , WIND DANIEL , DECUSATIS CASIMIR M , VERPLANKEN FABRICE JEAN
IPC: H04L12/743
Abstract: Ein verbessertes Computersystem kann eine Steuereinheit enthalten, die einen Computerprozessor enthält. Das System kann auch eine Auswählervorrichtung in Datenaustausch mit der Steuereinheit enthalten, um durch die Auswählervorrichtung eine Tabelle mit einem höheren Kollisionsqualitätsindex als andere betrachtete Tabellen zu wählen. Das System kann weiterhin eine Austauschervorrichtung enthalten, um eine Standby-Tabelle zu konfigurieren, welche die durch die Auswählervorrichtung gewählte Tabelle ersetzt. Das System kann zusätzlich einen Switch enthalten, der eine Hash-Funktion auf der Grundlage des Ersetzens der gewählten Tabelle durch die Austauschervorrichtung ändert, um die Steuereinheit in die Lage zu versetzen, Einfügungszeiten und/oder Kollisionen zu verringern, wenn eine Verbindung mit neuen der Steuereinheit vorgestellten Komponenten hergestellt wird.
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