公开(公告)号：DE10053965A1

公开(公告)日：2002-06-20

申请号：DE10053965

申请日：2000-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  LAMMERS STEFAN ,  FREITAG MARTIN ,  ROEHR THOMAS

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: The arrangement has memory cells in a field in at least one plane at intersection points between word or programming lines and bit lines. Providing programming currents to word and bit lines corresponding to a selected cell causes stray magnetic fields in adjacent cells. The method involves feeding a compensation current to the adjacent cell word, programming, bit or special line to produce a compensation magnetic field countering the stray field. The MRAM arrangement has memory cells (11-13) in a memory cell field in at least one plane at intersection points between word lines (WL1) or programming lines and bit lines (BL1-BL3). Providing programming currents to word and bit lines corresponding to a selected cell causes stray magnetic fields in adjacent cells. The method involves feeding a compensation current to the word line or programming line or bit line or a special line of the adjacent cell(s) to produce a compensation magnetic field countering the stray field.

公开(公告)号：DE10032271A1

公开(公告)日：2002-01-24

申请号：DE10032271

申请日：2000-07-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  KANDOLF HELMUT ,  LAMMERS STEFAN

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: A magneto-resistive random access memory (MRAM) configuration is described in which line driver circuits are respectively assigned via connecting nodes to two memory cell arrays, with the result that the area for the driver circuits can practically be halved. Therefore a space-saving architecture and a more efficient MRAM configuration is obtained.

公开(公告)号：DE10014385A1

公开(公告)日：2001-10-04

申请号：DE10014385

申请日：2000-03-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MANYOKI ZOLTAN ,  ESTERL ROBERT ,  BOEHM THOMAS ,  LAMMERS STEFAN

IPC: G05F3/24 ,  H01L23/58 ,  H01L27/085 ,  H03H11/00

Abstract: The voltage divider includes a first chain (A) comprising series-connected, n-type MOS transistors (N0-N4), of similar dimensions and similar gate-source voltages and which operate in the linear region. The voltage to be divided is applied to the ends of the chain, and the divided voltages are available at the respective source terminals. A second chain (B) of MOS transistors (P0-P4), complementary to the first transistors has the same dimensions and number as the first chain. The transistors of the first chain are connected to the transistors of the second chain. Each transistor chain (A,B) produces the gate-source bias voltage for the other transistors chain (B,A).